Semiconductor device and manufacturing method thereof

ABSTRACT

A semiconductor device includes a first oxide insulating layer over a first insulating layer, an oxide semiconductor layer over the first oxide insulating layer, a source electrode layer and a drain electrode layer over the oxide semiconductor layer, a second insulating layer over the source electrode layer and the drain electrode layer, a second oxide insulating layer over the oxide semiconductor layer, a gate insulating layer over the second oxide insulating layer, a gate electrode layer over the gate insulating layer, and a third insulating layer over the second insulating layer, the second oxide insulating layer, the gate insulating layer, and the gate electrode layer. A side surface portion of the second insulating layer is in contact with the second oxide insulating layer. The gate electrode layer includes a first region and a second region. The first region has a width larger than that of the second region.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.14/995,562, filed Jan. 14, 2016, now allowed, which claims the benefitof foreign priority applications filed in Japan on Jan. 26, 2015 asJapanese Patent Application Serial No. 2015-012713, filed in Japan onJan. 26, 2015 Japanese Patent Application Serial No. 2015-012718, filedin Japan on Feb. 27, 2015 as Japanese Patent Application Serial No.2015-039161, filed in Japan on Mar. 3, 2015 as Japanese PatentApplication Serial No. 2015-041682, filed in Japan on Mar. 10, 2015 asJapanese Patent Application Serial No. 2015-046870, and filed in Japanon Mar. 17, 2015 as Japanese Patent Application Serial No. 2015-053100,the entire contents of which are hereby incorporated by reference, allof which are incorporated by reference.

TECHNICAL FIELD

The present invention relates to an object, a method, or a manufacturingmethod. In addition, the present invention relates to a process, amachine, manufacture, or a composition of matter. In particular, thepresent invention relates to, for example, a semiconductor device, adisplay device, a light-emitting device, a power storage device, animaging device, a driving method thereof, or a manufacturing methodthereof.

In this specification and the like, a semiconductor device generallymeans a device that can function by utilizing semiconductorcharacteristics. A transistor and a semiconductor circuit areembodiments of semiconductor devices. In some cases, a memory device, adisplay device, or an electronic device includes a semiconductor device.

BACKGROUND ART

A technique by which a transistor is formed using a semiconductor filmformed over a substrate having an insulating surface has been attractingattention. The transistor is used in a wide range of electronic devicessuch as an integrated circuit (IC) or an image display device (displaydevice). A silicon-based semiconductor material is widely known as amaterial for a semiconductor thin film that can be used for atransistor. As another material, an oxide semiconductor has beenattracting attention.

For example, a transistor whose active layer includes an amorphous oxidesemiconductor containing indium (In), gallium (Ga), and zinc (Zn) isdisclosed in Patent Document 1.

REFERENCE Patent Document

-   [Patent Document 1] Japanese Published Patent Application No.    2006-165528

DISCLOSURE OF INVENTION

In miniaturization of a semiconductor element, the parasitic capacitanceof a transistor is a major problem.

In the case where parasitic capacitance exists in a channel (e.g.,between a source electrode and a drain electrode) and the vicinity ofthe channel, a time for charging the parasitic capacitance is needed inthe transistor operation; thus, not only the responsiveness of thetransistor but the responsiveness of the semiconductor device islowered.

It becomes more difficult to control various steps of manufacturingtransistors (in particular, film formation, processing, and the like) asthe miniaturization advances, and variations in the shapes of thetransistors significantly affect transistor characteristics andreliability.

Thus, an object of one embodiment of the present invention is to reducethe parasitic capacitance of a transistor. Another object is to providea semiconductor device with favorable electrical characteristics.Another object is to provide a highly reliable semiconductor device.Another object is to reduce variations in characteristics caused bymanufacturing steps of a transistor or a semiconductor device. Anotherobject is to provide a semiconductor device including an oxidesemiconductor layer having few oxygen vacancies. Another object is toprovide a semiconductor device that can be manufactured in a simpleprocess. Another object is to provide a semiconductor device with astructure in which the density of interface states in the vicinity ofthe oxide semiconductor layer can be reduced. Another object is toprovide a semiconductor device with low power consumption. Anotherobject is to provide a novel semiconductor device or the like. Anotherobject is to provide a manufacturing method of the semiconductor device.

Note that the description of these objects does not disturb theexistence of other objects. In one embodiment of the present invention,there is no need to achieve all the objects. Other objects will beapparent from and can be derived from the description of thespecification, the drawings, the claims, and the like.

One embodiment of the present invention is a semiconductor deviceincluding a first insulating layer, a first oxide insulating layer overthe first insulating layer, an oxide semiconductor layer over the firstoxide insulating layer, a source electrode layer and a drain electrodelayer over the oxide semiconductor layer, a second insulating layer overthe first insulating layer, the source electrode layer, the drainelectrode layer, and the oxide semiconductor layer, a second oxideinsulating layer over the oxide semiconductor layer, a gate insulatinglayer over the second oxide insulating layer, a gate electrode layerover the gate insulating layer, and a third insulating layer over thesecond insulating layer, the second oxide insulating layer, the gateinsulating layer, and the gate electrode layer. A side surface portionof the second insulating layer is in contact with the second oxideinsulating layer. The gate electrode layer includes a first region and asecond region that have different widths. The first region is locatedover the second region. The first region has a width larger than that ofthe second region.

In addition, in the gate electrode layer, a side surface portion of thegate electrode layer includes at least one inflection point in a crosssection parallel to a thickness direction of the gate electrode layer.

In addition, in the gate electrode layer, a side surface portion of thefirst region extends beyond a tangent of a side surface portion of thesecond region.

In addition, the side surface portion of the gate electrode layerincludes two or more taper angles.

Another embodiment of the present invention is a semiconductor deviceincluding a first insulating layer, a first oxide insulating layer overthe first insulating layer, an oxide semiconductor layer over the firstoxide insulating layer, a source electrode layer and a drain electrodelayer over the oxide semiconductor layer, a second insulating layer overthe first insulating layer, the source electrode layer, the drainelectrode layer, and the oxide semiconductor layer, a second oxideinsulating layer over the oxide semiconductor layer, a gate insulatinglayer over the second oxide insulating layer, a gate electrode layerover the gate insulating layer, and a third insulating layer over thesecond insulating layer, the second oxide insulating layer, the gateinsulating layer, and the gate electrode layer. A side surface portionof the second insulating layer is in contact with the second oxideinsulating layer. The gate electrode layer includes a first region, asecond region, and a third region that have different widths. The firstregion is located over the second region and the third region. Thesecond region is located over the third region. The third region has awidth larger than that in a lower portion of the second region.

In addition, a side surface portion of the first region or the thirdregion of the gate electrode layer preferably extends beyond a tangentformed in the second region of the gate electrode layer.

In addition, a side surface portion of the gate electrode layerpreferably includes two or more inflection points.

In addition, the side surface portion of the gate electrode layerpreferably includes three or more taper angles.

Another embodiment of the present invention is a method formanufacturing a semiconductor device including the steps of forming afirst insulating layer, forming a first oxide insulating film over thefirst insulating layer, forming an oxide semiconductor film over thefirst oxide insulating film, forming a first conductive film over theoxide semiconductor film, forming a first oxide insulating layer and anoxide semiconductor layer by selectively etching the first oxideinsulating film and the oxide semiconductor film using a first resistmask and the first conductive film, forming a second insulating filmover the first insulating layer and the first conductive film, forming asecond insulating layer by performing planarization treatment on thesecond insulating film, forming a groove by selectively etching thesecond insulating layer using a second resist mask, forming a sourceelectrode layer and a drain electrode layer by selectively etching thefirst conductive film using the second resist mask and the secondinsulating layer, forming a second oxide insulating film over the secondinsulating layer and the oxide semiconductor layer, forming a thirdinsulating film over the second oxide insulating film, forming a secondconductive film over the third insulating film, forming a second oxideinsulating layer, a gate insulating layer, and a gate electrode layer byperforming planarization treatment on the second conductive film, thethird insulating film, and the second oxide insulating film, and forminga fourth insulating layer over the second oxide insulating layer, thegate insulating layer, and the gate electrode layer.

In addition, at the time of forming the groove, it is preferable thatthe shape of the second resist mask be changed to form a third resistmask protruding from the side surface portion of the second insulatinglayer, the second insulating layer be selectively etched using the thirdresist mask, and the side surface portion of the second insulating layerhave one or more inflection points in a cross section parallel to athickness direction of the gate electrode layer.

Another embodiment of the present invention is a method formanufacturing a semiconductor device including the steps of forming afirst insulating layer, forming a first oxide insulating film over thefirst insulating layer, forming an oxide semiconductor film over thefirst oxide insulating film, forming a first conductive film over theoxide semiconductor film, forming a first oxide insulating layer and anoxide semiconductor layer by selectively etching the first oxideinsulating film and the oxide semiconductor film using a first resistmask and the first conductive film, forming a second insulating filmover the first insulating layer and the first conductive film, forming asecond insulating layer by performing planarization treatment on thesecond insulating film, forming a groove by selectively etching thesecond insulating layer using a second resist mask, selectively etchingthe first conductive film using the second resist mask and the secondinsulating layer, forming a source electrode layer and a drain electrodelayer such that a distance between the source and drain electrode layersis larger than a width between lower ends of side surfaces of the secondinsulating layer by etching the first conductive film in a directionsubstantially perpendicular to a substrate surface, forming a secondoxide insulating film to be in contact with a top surface of the oxidesemiconductor layer, part of a top surface, a side surface portion, anda bottom surface of the second insulating layer, the source electrodelayer, and the drain electrode layer, forming a third insulating filmover the second oxide insulating film, forming a second conductive filmover the third insulating film, forming a second oxide insulating layer,a gate insulating layer, and a gate electrode layer by performingplanarization treatment on the second conductive film, the thirdinsulating film, and the second oxide insulating film, and forming afourth insulating layer over the second oxide insulating layer, the gateinsulating layer, and the gate electrode layer.

In addition, at the time of forming the groove, it is preferable thatthe shape of the second resist mask be changed to form a third resistmask protruding from the side surface portion of the second insulatinglayer, the second insulating layer be selectively etched using the thirdresist mask, and the side surface portion of the second insulating layerhave one or more inflection points in a cross section parallel to athickness direction of the gate electrode layer.

Any of the aforementioned semiconductor devices can be combined with amicrophone, a speaker, and a housing.

According to one embodiment of the present invention, the parasiticcapacitance of a transistor can be reduced. Alternatively, asemiconductor device with favorable electrical characteristics can beprovided. Alternatively, a highly reliable semiconductor device can beprovided. Alternatively, variations in characteristics caused bymanufacturing steps of a transistor or a semiconductor device can bereduced. Alternatively, a semiconductor device including an oxidesemiconductor layer having few oxygen vacancies can be provided.Alternatively, a semiconductor device that can be manufactured in asimple process can be provided. Alternatively, a semiconductor devicewith a structure in which the density of interface states in thevicinity of the oxide semiconductor layer can be reduced can beprovided. Alternatively, a semiconductor device with low powerconsumption can be provided. Alternatively, a novel semiconductor deviceor the like can be provided. Alternatively, a manufacturing method ofthe semiconductor device can be provided.

Note that the description of these effects does not disturb theexistence of other effects. One embodiment of the present invention doesnot necessarily have all the effects listed above. Other effects will beapparent from and can be derived from the description of thespecification, the drawings, the claims, and the like.

BRIEF DESCRIPTION OF DRAWINGS

In the accompanying drawings:

FIGS. 1A and 1B are a top view and a cross-sectional view illustrating atransistor;

FIG. 2 is an enlarged cross-sectional view of a transistor;

FIGS. 3A and 3B are a cross-sectional view and a band diagram of oxidelayers;

FIGS. 4A to 4D illustrate an ALD deposition mechanism;

FIGS. 5A and 5B are schematic views of an ALD apparatus;

FIGS. 6A and 6B are a top view and a cross-sectional view illustrating amethod for manufacturing a transistor;

FIGS. 7A and 7B are a top view and a cross-sectional view illustrating amethod for manufacturing a transistor;

FIGS. 8A and 8B are a top view and a cross-sectional view illustrating amethod for manufacturing a transistor;

FIGS. 9A and 9B are a top view and a cross-sectional view illustrating amethod for manufacturing a transistor;

FIGS. 10A and 10B are a top view and a cross-sectional view illustratinga method for manufacturing a transistor;

FIGS. 11A and 11B are a top view and a cross-sectional view illustratinga method for manufacturing a transistor;

FIGS. 12A and 12B are a top view and a cross-sectional view illustratinga method for manufacturing a transistor;

FIGS. 13A and 13B are a top view and a cross-sectional view illustratinga transistor;

FIGS. 14A and 14B are a top view and a cross-sectional view illustratinga transistor;

FIGS. 15A to 15C are enlarged cross-sectional views of transistors;

FIGS. 16A and 16B are a top view and a cross-sectional view illustratinga transistor;

FIGS. 17A and 17B are enlarged cross-sectional views of transistors;

FIGS. 18A and 18B are a top view and a cross-sectional view illustratinga method for manufacturing a transistor;

FIGS. 19A and 19B are a top view and a cross-sectional view illustratinga method for manufacturing a transistor;

FIGS. 20A and 20B are a top view and a cross-sectional view illustratinga method for manufacturing a transistor;

FIGS. 21A and 21B are a top view and a cross-sectional view illustratinga method for manufacturing a transistor;

FIGS. 22A to 22D are Cs-corrected high-resolution TEM images of a crosssection of a CAAC-OS and a cross-sectional schematic view of theCAAC-OS;

FIGS. 23A to 23D are Cs-corrected high-resolution TEM images of a planeof a CAAC-OS;

FIGS. 24A to 24C show structural analysis of a CAAC-OS and a singlecrystal oxide semiconductor by XRD;

FIGS. 25A and 25B show electron diffraction patterns of a CAAC-OS;

FIG. 26 shows a change of crystal parts of In—Ga—Zn oxide owing toelectron irradiation;

FIGS. 27A to 27D are cross-sectional views and circuit diagrams of asemiconductor device;

FIGS. 28A to 28C are a cross-sectional view and circuit diagrams of asemiconductor device;

FIGS. 29A and 29B are plan views of an imaging device;

FIGS. 30A and 30B are plan views of pixels of an imaging device;

FIGS. 31A and 31B are cross-sectional views of an imaging device;

FIGS. 32A and 32B are cross-sectional views of an imaging device;

FIG. 33 illustrates a configuration example of an RF tag;

FIG. 34 illustrates a structure example of a CPU;

FIG. 35 is a circuit diagram of a memory element;

FIGS. 36A to 36C illustrate a configuration example of a display deviceand circuit diagrams of pixels;

FIG. 37 illustrates a display module;

FIGS. 38A and 38B are perspective views illustrating a cross-sectionalstructure of a package using a lead frame interposer;

FIGS. 39A to 39E are diagrams illustrating electronic devices;

FIGS. 40A to 40D are diagrams illustrating electronic devices;

FIGS. 41A to 41C are diagrams illustrating electronic devices;

FIGS. 42A to 42F are diagrams illustrating electronic devices;

FIG. 43 is a cross-sectional view of a manufactured transistor;

FIGS. 44A and 44B are cross-sectional views of a manufacturedtransistor;

FIG. 45 shows measurement results of Ids-Vgs characteristics offabricated transistors;

FIG. 46 shows measurement results of Ids-Vgs characteristics of afabricated transistor;

FIG. 47 shows measurement results of Ids-Vgs characteristics offabricated transistors;

FIG. 48 shows reliability test results of fabricated transistors;

FIG. 49 is a top view of a fabricated TEG;

FIG. 50 is a top view of a fabricated TEG;

FIG. 51 is a top view of a fabricated TEG;

FIG. 52 shows measurement results of frequency characteristics offabricated transistors;

FIGS. 53A and 53B are cross-sectional views of a fabricated transistor;

FIG. 54 is a cross-sectional view of a fabricated transistor;

FIG. 55 shows measurement results of frequency characteristics of afabricated transistor;

FIG. 56 shows measurement results of off-leakage current of fabricatedtransistors; and

FIG. 57 shows Id-Vg measurement results of fabricated transistors.

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiments will be described in detail with reference to the drawings.Note that the present invention is not limited to the followingdescription. It will be readily appreciated by those skilled in the artthat modes and details of the present invention can be modified invarious ways without departing from the spirit and scope of the presentinvention. The present invention therefore should not be construed asbeing limited to the following description of the embodiments. Instructures of the invention described below, the same portions orportions having similar functions are denoted by the same referencenumerals in different drawings, and the description thereof is notrepeated in some cases. The same components are denoted by differenthatching patterns in different drawings, or the hatching patterns areomitted in some cases.

For example, in this specification and the like, an explicit description“X and Y are connected” means that X and Y are electrically connected, Xand Y are functionally connected, and X and Y are directly connected.Accordingly, without being limited to a predetermined connectionrelationship, for example, a connection relationship shown in drawingsor texts, another connection relationship is included in the drawings orthe texts.

Here, each ofX and Y denotes an object (e.g., a device, an element, acircuit, a wiring, an electrode, a terminal, a conductive film, or alayer).

Examples of the case where X and Y are directly connected include thecase where an element that enables electrical connection betweenXand Y(e.g., a switch, a transistor, a capacitor, an inductor, a resistor, adiode, a display element, a light-emitting element, or a load) is notconnected between X and Y, and the case where X and Y are connectedwithout the element that enables electrical connection between X and Yprovided therebetween.

For example, in the case where X and Y are electrically connected, oneor more elements that enable electrical connection between X and Y(e.g., a switch, a transistor, a capacitor, an inductor, a resistor, adiode, a display element, a light-emitting element, or a load) can beconnected between X and Y. Note that the switch is controlled to beturned on or off. That is, the switch is conducting or not conducting(is turned on or off) to determine whether current flows therethrough ornot. Alternatively, the switch has a function of selecting and changinga current path. Note that the case where X and Y are electricallyconnected includes the case where X and Y are directly connected.

For example, in the case where X and Y are functionally connected, oneor more circuits that enable functional connection betweenXand Y (e.g.,a logic circuit such as an inverter, a NAND circuit, or a NOR circuit; asignal converter circuit such as a D/A converter circuit, an A/Dconverter circuit, or a gamma correction circuit; a potential levelconverter circuit such as a power supply circuit (e.g., a step-upcircuit or a step-down circuit) or a level shifter circuit for changingthe potential level of a signal; a voltage source; a current source; aswitching circuit; an amplifier circuit such as a circuit that canincrease signal amplitude, the amount of current, or the like, anoperational amplifier, a differential amplifier circuit, a sourcefollower circuit, or a buffer circuit; a signal generation circuit; astorage circuit; or a control circuit) can be connected between X and Y.Note that for example, in the case where a signal output from X istransmitted to Y even when another circuit is provided between X and Y,X and Y are functionally connected. The case where X and Y arefunctionally connected includes the case where X and Y are directlyconnected and X and Y are electrically connected.

Note that in this specification and the like, an explicit description “Xand Y are electrically connected” means that X and Y are electricallyconnected (i.e., the case where X and Y are connected with anotherelement or another circuit provided therebetween), X and Y arefunctionally connected (i.e., the case where X and Y are functionallyconnected with another circuit provided therebetween), and X and Y aredirectly connected (i.e., the case where X and Y are connected withoutanother element or another circuit provided therebetween). That is, inthis specification and the like, the explicit description “X and Y areelectrically connected” is the same as the explicit description “X and Yare connected.”

For example, the case where a source (or a first terminal or the like)of a transistor is electrically connected to X through (or not through)Z1 and a drain (or a second terminal or the like) of the transistor iselectrically connected to Y through (or not through) Z2, or the casewhere a source (or a first terminal or the like) of a transistor isdirectly connected to part of Z1 and another part of Z1 is directlyconnected to X while a drain (or a second terminal or the like) of thetransistor is directly connected to part of Z2 and another part of Z2 isdirectly connected to Y, can be expressed by using any of the followingexpressions.

The expressions include, for example, “X, Y, a source (or a firstterminal or the like) of a transistor, and a drain (or a second terminalor the like) of the transistor are electrically connected to each other,and X, the source (or the first terminal or the like) of the transistor,the drain (or the second terminal or the like) of the transistor, and Yare electrically connected to each other in that order,” “a source (or afirst terminal or the like) of a transistor is electrically connected toX, a drain (or a second terminal or the like) of the transistor iselectrically connected to Y, and X, the source (or the first terminal orthe like) of the transistor, the drain (or the second terminal or thelike) of the transistor, and Y are electrically connected to each otherin that order,” and “X is electrically connected to Y through a source(or a first terminal or the like) and a drain (or a second terminal orthe like) of a transistor, and X, the source (or the first terminal orthe like) of the transistor, the drain (or the second terminal or thelike) of the transistor, and Y are connected in that order.” When theconnection order in a circuit structure is defined by an expressionsimilar to the above examples, a source (or a first terminal or thelike) and a drain (or a second terminal or the like) of a transistor canbe distinguished from each other to specify the technical scope.

Other examples of the expressions include “a source (or a first terminalor the like) of a transistor is electrically connected to Xthrough atleast a first connection path, the first connection path does notinclude a second connection path, the second connection path is a pathbetween the source (or the first terminal or the like) of the transistorand a drain (or a second terminal or the like) of the transistor, Z1 ison the first connection path, the drain (or the second terminal or thelike) of the transistor is electrically connected to Y through at leasta third connection path, the third connection path does not include thesecond connection path, and Z2 is on the third connection path.” It isalso possible to use the expression “a source (or a first terminal orthe like) of a transistor is electrically connected to Xthrough at leastZ1 on a first connection path, the first connection path does notinclude a second connection path, the second connection path includes aconnection path through the transistor, a drain (or a second terminal orthe like) of the transistor is electrically connected to Y through atleast Z2 on a third connection path, and the third connection path doesnot include the second connection path.” Still another example of theexpressions is “a source (or a first terminal or the like) of atransistor is electrically connected to Xthrough at least Z1 on a firstelectrical path, the first electrical path does not include a secondelectrical path, the second electrical path is an electrical path fromthe source (or the first terminal or the like) of the transistor to adrain (or a second terminal or the like) of the transistor, the drain(or the second terminal or the like) of the transistor is electricallyconnected to Y through at least Z2 on a third electrical path, the thirdelectrical path does not include a fourth electrical path, and thefourth electrical path is an electrical path from the drain (or thesecond terminal or the like) of the transistor to the source (or thefirst terminal or the like) of the transistor.” When the connection pathin a circuit structure is defined by an expression similar to the aboveexamples, a source (or a first terminal or the like) and a drain (or asecond terminal or the like) of a transistor can be distinguished fromeach other to specify the technical scope.

Note that these expressions are examples and there is no limitation onthe expressions. Here, X, Y, Z1, and Z2 each denote an object (e.g., adevice, an element, a circuit, a wiring, an electrode, a terminal, aconductive film, or a layer).

Even when independent components are electrically connected to eachother in a circuit diagram, one component has functions of a pluralityof components in some cases. For example, when part of a wiring alsofunctions as an electrode, one conductive film functions as the wiringand the electrode. Thus, the term “electrical connection” in thisspecification also means such a case where one conductive film hasfunctions of a plurality of components.

<Notes on the Description for Drawings>

In this specification, terms for describing arrangement, such as “over”and “under”, are used for convenience to describe a positional relationbetween components with reference to drawings. Furthermore, thepositional relation between components is changed as appropriate inaccordance with a direction in which each component is described. Thus,there is no limitation on terms used in this specification, anddescription can be made appropriately depending on the situation.

The term “over” or “below” does not necessarily mean that a component isplaced directly on or directly below and directly in contact withanother component. For example, the expression “electrode B overinsulating layer A” does not necessarily mean that the electrode B is onand in direct contact with the insulating layer A and can mean the casewhere another component is provided between the insulating layer A andthe electrode B.

In this specification, the term “parallel” indicates that the angleformed between two straight lines is greater than or equal to −10° andless than or equal to 10°, and accordingly also includes the case wherethe angle is greater than or equal to −5° and less than or equal to 5°.The term “substantially parallel” indicates that the angle formedbetween two straight lines is greater than or equal to −30° and lessthan or equal to 30°. The term “perpendicular” indicates that the angleformed between two straight lines is greater than or equal to 80° andless than or equal to 100°, and accordingly includes the case where theangle is greater than or equal to 85° and less than or equal to 95°. Theterm “substantially perpendicular” indicates that the angle formedbetween two straight lines is greater than or equal to 60° and less thanor equal to 120°.

In this specification, trigonal and rhombohedral crystal systems areincluded in a hexagonal crystal system.

In drawings, the size, the layer thickness, or the region is determinedarbitrarily for description convenience. Therefore, the size, the layerthickness, or the region is not limited to the illustrated scale. Notethat the drawings are schematically shown for clarity, and embodimentsof the present invention are not limited to shapes or values shown inthe drawings.

In drawings such as plan views (also referred to as layout views) andperspective views, some of components might not be illustrated forclarity of the drawings.

The expression “being the same” may refer to having the same area orhaving the same shape. In addition, the expression “being the same”include a case of “being substantially the same” because a manufacturingprocess might cause some differences.

<Notes on Expressions that can be Rephrased>

In this specification and the like, in describing connections of atransistor, expressions “one of a source and a drain” (or a firstelectrode or a first terminal) and “the other of the source and thedrain” (or a second electrode or a second terminal) are used. This isbecause a source and a drain of a transistor are interchangeabledepending on the structure, operation conditions, or the like of thetransistor. Note that the source or the drain of the transistor can alsobe referred to as a source (or drain) terminal, a source (or drain)electrode, or the like as appropriate depending on the situation.

In addition, in this specification and the like, the term such as an“electrode” or a “wiring” does not limit a function of the component.For example, an “electrode” is used as part of a “wiring” in some cases,and vice versa. Further, the term “electrode” or “wiring” can also meana combination of a plurality of “electrodes” and “wirings” formed in anintegrated manner.

In this specification and the like, a transistor is an element having atleast three terminals: a gate, a drain, and a source. The transistor hasa channel region between the drain (a drain terminal, a drain region, ora drain electrode) and the source (a source terminal, a source region,or a source electrode), and current can flow through the drain, thechannel region, and the source.

Since the source and the drain of the transistor change depending on thestructure, operating conditions, and the like of the transistor, it isdifficult to define which is a source or a drain. Thus, a portion thatfunctions as a source or a portion is not referred to as a source or adrain in some cases. In that case, one of the source and the drain mightbe referred to as a first electrode, and the other of the source and thedrain might be referred to as a second electrode.

In this specification, ordinal numbers such as first, second, and thirdare used to avoid confusion among components, and thus do not limit thenumber of the components.

In this specification and the like, a structure in which a flexibleprinted circuit (FPC), a tape carrier package (TCP), or the like isattached to a substrate of a display panel, or a structure in which anintegrated circuit (IC) is directly mounted on a substrate by a chip onglass (COG) method is referred to as a display device in some cases.

Note that the terms “film” and “layer” can be interchanged with eachother depending on the case or circumstances. For example, the term“conductive layer” can be changed into the term “conductive film” insome cases. In addition, the term “insulating film” can be changed intothe term “insulating layer” in some cases.

<Notes on Definitions of Terms>

Definitions of terms that are not mentioned in the above embodiments aredescribed below.

In this specification, the term “trench” or “groove” refers to adepression with a narrow belt shape.

In addition, the term “inflection point” refers to a point at which thedirection of a tangent is changed when the tangent is drawn at one pointof a side surface portion of a structure including a “film” and a“layer”.

Moreover, in this specification, an angle formed by a plane which isparallel to a substrate and a side surface portion of an object isreferred to as a taper angle.

<Connection>

In this specification, when it is described that “A and B are connectedto each other”, the case where A and B are electrically connected toeach other is included in addition to the case whereA and B are directlyconnected to each other. Here, the expression “A and B are electricallyconnected” means the case where electric signals can be transmitted andreceived between A and B when an object having any electric actionexists between A and B.

Note that these expressions are examples and there is no limitation onthe expressions. Here, X, Y, Z1, and Z2 each denote an object (e.g., adevice, an element, a circuit, a wiring, an electrode, a terminal, aconductive film, and a layer).

Note that a content (or may be part of the content) described in oneembodiment may be applied to, combined with, or replaced by a differentcontent (or may be part of the different content) described in theembodiment and/or a content (or may be part of the content) described inone or a plurality of different embodiments.

Note that in each embodiment, a content described in the embodiment is acontent described with reference to a variety of diagrams or a contentdescribed with a text described in this specification.

Note that by combining a diagram (or may be part of the diagram)illustrated in one embodiment with another part of the diagram, adifferent diagram (or may be part of the different diagram) illustratedin the embodiment, and/or a diagram (or may be part of the diagram)illustrated in one or a plurality of different embodiments, much morediagrams can be formed.

Embodiment 1

In this embodiment, a semiconductor device of one embodiment of thepresent invention and a manufacturing method of the semiconductor deviceare described with reference to drawings.

FIGS. 1A and 1B are a top view and a cross-sectional view whichillustrate a transistor 10 of one embodiment of the present invention.FIG. 1A is a top view and FIG. 1B is a cross-sectional view taken alongdashed-dotted line A1-A2 and dashed-dotted line A3-A4 in FIG. 1A.

In FIG. 1A, some components are scaled up or down or omitted for easyunderstanding. In some cases, the direction of the dashed-dotted lineA1-A2 is referred to as a channel length direction, and the direction ofthe dashed-dotted line A3-A4 is referred to as a channel widthdirection.

The transistor 10 includes a substrate 100, an insulating layer 110, anoxide insulating layer 121, an oxide semiconductor layer 122, an oxideinsulating layer 123, a source electrode layer 130, a drain electrodelayer 140, a gate insulating layer 150, a gate electrode layer 160, aninsulating layer 175, and an insulating layer 170. The insulating layer110 is formed over the substrate 100. The oxide insulating layer 121 isformed over the insulating layer 110. The oxide semiconductor layer 122is formed over the oxide insulating layer 121. The source electrodelayer 130 and the drain electrode layer 140 are formed over andelectrically connected to the oxide semiconductor layer 122. Theinsulating layer 175 is formed over the insulating layer 110, the sourceelectrode layer 130, and the drain electrode layer 140, and is incontact with side surface portions of the oxide insulating layer 121 andthe oxide semiconductor layer 122. The oxide insulating layer 123 isformed over the oxide semiconductor layer 122. In addition, the oxideinsulating layer 123 is in contact with side surfaces of the insulatinglayer 175, the source electrode layer 130, and the drain electrode layer140. The gate insulating layer 150 is formed over the oxide insulatinglayer 123. The gate electrode layer 160 is formed over the gateinsulating layer 150. The insulating layer 170 is formed over the gateelectrode layer 160, the gate insulating layer 150, the oxide insulatinglayer 123, and the insulating layer 175.

<Oxide Insulating Layer>

An oxide insulating layer (e.g., the oxide insulating layer 121 and theoxide insulating layer 123) refers to a layer which basically has aninsulating property and in which current can flow through the interfacewith the semiconductor layer and the vicinity thereof when a gateelectric field or a drain electric field is increased.

Although the gate electrode layer 160 is a single layer in FIG. 1B, itmay be a stacked layer of a gate electrode layer 161 and a gateelectrode layer 162, which will be described in Embodiment 2. In thetransistor 10, end portions of the oxide insulating layer 123 and thegate insulating layer 150 are located on the outer side of the gateelectrode layer 160. In addition, an insulating layer formed using anoxide may be provided over the insulating layer 170. The insulatinglayer is provided as needed and another insulating layer may be furtherprovided thereover. The structure described here has a high heatdissipation effect: heat generated in the oxide insulating layer 121,the oxide semiconductor layer 122, and the oxide insulating layer 123 bythe operation of the transistor 10 can be sufficiently released becausethe oxide semiconductor layer 122 and the oxide insulating layer 123 arein contact with the source electrode layer 130 and the drain electrodelayer 140.

In the transistor 10, in the channel width direction, the gate electrodelayer 160 faces the side surfaces of the oxide insulating layer 121, theoxide semiconductor layer 122, and the oxide insulating layer 123 withthe gate insulating layer 150 provided therebetween as illustrated inthe cross-sectional view taken along line A3-A4 in FIG. 1B. That is, theoxide insulating layer 121, the oxide semiconductor layer 122, and theoxide insulating layer 123 are surrounded by the electric field of thegate electrode layer 160 in the channel width direction when voltage isapplied to the gate electrode layer 160. The transistor structure inwhich a semiconductor layer is surrounded by the electric field of thegate electrode layer 160 is referred to as a surrounded channel(s-channel) structure. Furthermore, the gate electrode, the sourceelectrode, and the drain electrode of the transistor 10 can be formed ina self-aligned manner; thus, alignment accuracy can be improved andminiaturized transistors can be easily manufactured. Note that such astructure is referred to as a self-aligned (SA) s-channel FET structure,a trench-gate s-channel FET structure, a trench-gate self-aligned (TGSA)s-channel FET structure, or a gate-last s-channel FET structure.

Here, the oxide insulating layer 121, the oxide semiconductor layer 122,and the oxide insulating layer 123 are collectively referred to as anoxide semiconductor layer 120. When a transistor having the SA s-channelstructure (SA s-channel transistor) is in an on state, a channel isformed in the entire oxide semiconductor layer 120 (bulk), so that theon-state current increases. When the SA s-channel transistor is in anoff state, the entire channel region formed in the oxide semiconductorlayer 120 is depleted; as a result, the off-state current can be furtherreduced.

FIG. 2 is an enlarged view of the transistor 10. The transistor 10includes the oxide insulating layer 123, the gate insulating layer 150,and the gate electrode layer 160 in a groove portion 174. The gateelectrode layer 160 has a first region 171 and a second region 172 thathave different widths in a cross section of the groove portion 174 inthe channel length direction. A width L1 in the first region 171 islarger than a width L2 in the second region 172. Note that the firstregion 171 is located over the second region 172.

In the case where an angle formed by a plane which is parallel to asubstrate and a side surface portion of the gate electrode layer 160 isreferred to as a taper angle, the side surface portion of the gateelectrode layer 160 of the transistor 10 has a first taper angle θ1 inthe first region 171 and a second taper angle θ2 in the second region172. In addition, the cross section of the gate electrode layer 160 hastwo inflection points (an inflection point P1 and an inflection pointP2) at which the curvature of the side surface portion is changed.Moreover, the side surface portion of the first region 171 of the gateelectrode layer 160 extends beyond a tangent T2 of the side surfaceportion of the second region 172.

With such a structure, when the oxide insulating layer 123, the gateinsulating layer 150, and the gate electrode layer 160 are formed in thegroove portion 174, the embeddability of each film can be improved, andthe transistor 10 can be easily manufactured.

In addition, the transistor 10 has the SA s-channel structure, wherebyparasitic capacitance generated between the gate electrode and thesource electrode or between the gate electrode and the drain electrodeis reduced, and the cut-off frequency characteristics of the transistor10 are improved. That is, high-speed response of the transistor 10 canbe achieved.

Note that the top surface of the source electrode layer 130 or the drainelectrode layer 140 may be located under, over, or at the same level asthe bottom surface of the gate electrode layer 160.

<Channel Length>

Note that the channel length refers to, for example, a distance betweena source (a source region or a source electrode) and a drain (a drainregion or a drain electrode) in a region where a semiconductor (or aportion where current flows in a semiconductor when a transistor is on)and a gate electrode overlap with each other or a region where a channelis formed in a top view of the transistor. In one transistor, channellengths in all regions are not necessarily the same value. In otherwords, the channel length of one transistor is not fixed to one value insome cases. Therefore, in this specification, the channel length is anyone of values, the maximum value, the minimum value, or the averagevalue in a region where a channel is formed.

<Channel Width>

Note that the channel width refers to, for example, the length of aregion where a semiconductor (or a portion where current flows in asemiconductor when a transistor is on) and a gate electrode overlap witheach other. In one transistor, channel widths in all regions are notnecessarily the same value. In other words, the channel width of onetransistor is not fixed to one value in some cases. Therefore, in thisspecification, the channel width is any one of values, the maximumvalue, the minimum value, or the average value in a region where achannel is formed.

Note that depending on transistor structures, a channel width in aregion where a channel is actually formed (hereinafter referred to as aneffective channel width) is different from a channel width shown in atop view of a transistor (hereinafter referred to as an apparent channelwidth) in some cases. For example, in a transistor having athree-dimensional structure, an effective channel width is greater thanan apparent channel width shown in a top view of the transistor, and itsinfluence cannot be ignored in some cases. For example, in aminiaturized transistor having a three-dimensional structure, theproportion of a channel region formed in a side surface of asemiconductor is high in some cases. In that case, an effective channelwidth obtained when a channel is actually formed is greater than anapparent channel width shown in the top view.

In a transistor having a three-dimensional structure, an effectivechannel width is difficult to measure in some cases. For example,estimation of an effective channel width from a design value requires anassumption that the shape of a semiconductor is known. Therefore,without accurate information on the shape of a semiconductor, it isdifficult to measure an effective channel width accurately.

<SCW>

Therefore, in this specification, in a top view of a transistor, anapparent channel width in a region where a semiconductor and a gateelectrode overlap with each other is referred to as a surrounded channelwidth (SCW) in some cases. Further, in this specification, in the casewhere the term “channel width” is simply used, it may denote asurrounded channel width or an apparent channel width. Alternatively, inthis specification, in the case where the term “channel width” is simplyused, it may denote an effective channel width in some cases. Note thatthe values of a channel length, a channel width, an effective channelwidth, an apparent channel width, a surrounded channel width, and thelike can be determined by obtaining and analyzing a cross-sectional TEMimage and the like.

Note that in the case where field-effect mobility, a current value perchannel width, and the like of a transistor are obtained by calculation,a surrounded channel width may be used for the calculation. In thatcase, a value different from the value obtained by calculation using aneffective channel width is obtained in some cases.

<Improvement of Characteristics in Miniaturization>

High integration of a semiconductor device requires miniaturization of atransistor. However, it is known that miniaturization of a transistorcauses deterioration of electrical characteristics of the transistor. Adecrease in channel width causes a reduction in on-state current.

In the transistor of one embodiment of the present invention shown inFIGS. 1A and 1B, for example, as described above, the oxide insulatinglayer 123 is formed so as to cover the oxide semiconductor layer 122where a channel is formed and the channel formation layer and the gateinsulating layer are not in contact with each other. Accordingly,scattering of carriers at the interface between the channel formationlayer and the gate insulating layer can be reduced and the on-statecurrent of the transistor can be increased.

In the transistor of one embodiment of the present invention, the gateelectrode layer 160 is formed to electrically surround the oxidesemiconductor layer 122, which is to be a channel, in the channel widthdirection; accordingly, a gate electric field is applied to the oxidesemiconductor layer 122 in the side surface direction in addition to theperpendicular direction. In other words, a gate electric field isapplied to the oxide semiconductor layer entirely, so that current flowsin the whole of the oxide semiconductor layer 122, leading to a furtherincrease in on-state current.

In the transistor of one embodiment of the present invention, the oxideinsulating layer 123 is formed over the oxide insulating layer 121 andthe oxide semiconductor layer 122, so that an interface state is lesslikely to be formed. In addition, impurities do not enter the oxidesemiconductor layer 122 from above and below because the oxideinsulating layer 121 is positioned between the insulating layer 110 andthe oxide semiconductor layer 122 and the oxide insulating layer 123 ispositioned between the gate insulating layer 150 and the oxidesemiconductor layer 122. Therefore, the transistor can achieve not onlythe increase in the on-state current of the transistor but alsostabilization of the threshold voltage and a reduction in the S value(subthreshold value). Thus, /cut (current when gate voltage VG is 0 V)can be reduced and power consumption can be reduced. Further, since thethreshold voltage of the transistor becomes stable, long-termreliability of the semiconductor device can be improved.

Although an example where a channel or the like is formed in the oxidesemiconductor layer 120 or the like is described in this embodiment, oneembodiment of the present invention is not limited thereto. For example,depending on cases or conditions, a channel, the vicinity of thechannel, a source region, a drain region, or the like may be formedusing a material containing silicon (including strained silicon),germanium, silicon germanium, silicon carbide, gallium arsenide,aluminum gallium arsenide, indium phosphide, gallium nitride, an organicsemiconductor, or the like.

<Structure of Transistor>

A structure of a transistor of this embodiment will be described.

<<Substrate 100>>

A glass substrate, a ceramic substrate, a quartz substrate, a sapphiresubstrate, or the like can be used as the substrate 100. Alternatively,a single crystal semiconductor substrate or a polycrystallinesemiconductor substrate of silicon or silicon carbide, a compoundsemiconductor substrate of silicon germanium, a silicon on insulator(SOI) substrate, or the like can be used. Still alternatively, any ofthese substrates provided with a semiconductor element may be used. Thesubstrate 100 is not limited to a simple supporting substrate, and maybe a substrate where a device such as a transistor is formed. In thatcase, one of the gate electrode layer 160, the source electrode layer130, and the drain electrode layer 140 of the transistor may beelectrically connected to the device.

Alternatively, a flexible substrate may be used as the substrate 100. Asa method for providing the transistor over a flexible substrate, thereis a method in which the transistor is formed over a non-flexiblesubstrate and then the transistor is separated and transferred to thesubstrate 100 that is a flexible substrate. In that case, a separationlayer is preferably provided between the non-flexible substrate and thetransistor. As the substrate 100, a sheet, a film, or a foil containinga fiber may be used. The substrate 100 may have elasticity. Thesubstrate 100 may have a property of returning to its original shapewhen bending or pulling is stopped. Alternatively, the substrate 100 mayhave a property of not returning to its original shape. The thickness ofthe substrate 100 is, for example, greater than or equal to 5 μm andless than or equal to 700 μm, preferably greater than or equal to 10 μmand less than or equal to 500 μm, or further preferably greater than orequal to 15 μm and less than or equal to 300 μm. When the substrate 100has a small thickness, the weight of the semiconductor device can bereduced. When the substrate 100 has a small thickness, even in the caseof using glass or the like, the substrate 100 may have elasticity or aproperty of returning to its original shape when bending or pulling isstopped. Therefore, an impact applied to the semiconductor device overthe substrate 100, which is caused by dropping or the like, can bereduced. That is, a durable semiconductor device can be provided.

For the substrate 100 which is a flexible substrate, metal, an alloy,resin, glass, or fiber thereof can be used, for example. The flexiblesubstrate 100 preferably has a lower coefficient of linear expansionbecause deformation due to an environment is suppressed. The flexiblesubstrate 100 is formed using, for example, a material whose coefficientof linear expansion is lower than or equal to 1×10⁻³/K, lower than orequal to 5×10⁻⁵/K, or lower than or equal to 1×10⁻⁵/K. Examples of theresin include polyester, polyolefin, polyamide (e.g., nylon or aramid),polyimide, polycarbonate, acrylic, and polytetrafluoroethylene (PTFE).In particular, aramid is preferably used for the flexible substrate 100because of its low coefficient of linear expansion.

<<Insulating Layer 110>>

The insulating layer 110 can have a function of supplying oxygen to theoxide semiconductor layer 120 as well as a function of preventingdiffusion of impurities from the substrate 100. For this reason, theinsulating layer 110 is preferably an insulating film containing oxygen,further preferably an insulating film having an oxygen content higherthan that in the stoichiometric composition. For example, the insulatinglayer 110 is a film of which the amount of released oxygen whenconverted into oxygen atoms is 1.0×10¹⁹ atoms/cm³ or more in TDSanalysis. Note that the temperature of the film surface in the TDSanalysis is preferably higher than or equal to 100° C. and lower than orequal to 700° C., or higher than or equal to 100° C. and lower than orequal to 500° C. In the case where the substrate 100 is provided withanother device as described above, the insulating layer 110 also has afunction of an interlayer insulating film. In that case, the insulatinglayer 110 is preferably subjected to planarization treatment such aschemical mechanical polishing (CMP) treatment so as to have a flatsurface.

<<Oxide Insulating Layer 121, Oxide Semiconductor Layer 122, and OxideInsulating Layer 123>>

The oxide semiconductor layer 122 is an oxide semiconductor filmcontaining In or Zn and typically contains In—Ga oxide, In—Zn oxide,In—Mg oxide, Zn—Mg oxide, or an In—M—Zn oxide (M is Al, Ti, Ga, Y, Zr,Sn, La, Ce, Mg, Hf, or Nd).

An oxide that can be used for each of the oxide insulating layer 121,the oxide semiconductor layer 122, and the oxide insulating layer 123preferably contains at least indium (In) or zinc (Zn). Alternatively,both In and Zn are preferably contained. In order to reduce variationsin electrical characteristics of the transistors including the oxidesemiconductor, the oxide semiconductor preferably contains a stabilizerin addition to In and Zn.

As a stabilizer, gallium (Ga), tin (Sn), hafnium (Hf), aluminum (Al),zirconium (Zr), and the like can be given. As another stabilizer,lanthanoid such as lanthanum (La), cerium (Ce), praseodymium (Pr),neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium(Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm),ytterbium (Yb), or lutetium (Lu) can be given.

Note that in the case where the oxide semiconductor layer 122 is anIn-M-Zn oxide, the atomic percentage of In may be greater than or equalto 50 atomic % and the atomic percentage of M may be less than 50 atomic%, when the summation of In and M is assumed to be 100 atomic %.

The indium and gallium contents in the oxide semiconductor layer 122 canbe compared with each other by time-of-flight secondary ion massspectrometry (TOF-SIMS), X-ray photoelectron spectrometry (XPS), orinductively coupled plasma mass spectrometry (ICP-MS).

Since the oxide semiconductor layer 122 has an energy gap of 2 eV ormore, preferably 2.5 eV or more, further preferably 3 eV or more, theoff-state current of the transistor 10 can be low.

The thickness of the oxide semiconductor layer 122 is greater than orequal to 3 nm and less than or equal to 200 nm, preferably greater thanor equal to 3 nm and less than or equal to 100 nm, further preferablygreater than or equal to 3 nm and less than or equal to 50 nm.

The oxide insulating layer 121 and the oxide insulating layer 123 eachcontain one or more elements contained in the oxide semiconductor layer122. Thus, interface scattering is unlikely to occur at the interfacesbetween the oxide semiconductor layer 122 and the oxide insulating layer121 and between the oxide semiconductor layer 122 and the oxideinsulating layer 123. The movement of carriers is not hindered at theinterfaces accordingly, and the transistor 10 can have high field-effectmobility.

Each of the oxide insulating layers 121 and 123 is typically In—Gaoxide, In—Zn oxide, In—Mg oxide, Ga—Zn oxide, Zn—Mg oxide, or an In-M-Znoxide (M is Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, Hf, or Nd), and has theenergy level at the conduction band minimum that is closer to a vacuumlevel than the energy level at the conduction band minimum of the oxidesemiconductor layer 122 is. Typically, a difference between the energylevel at the conduction band minimum of the oxide semiconductor layer122 and the energy level at the conduction band minimum of each of theoxide insulating layers 121 and 123 is greater than or equal to 0.05 eV,greater than or equal to 0.07 eV, greater than or equal to 0.1 eV, orgreater than or equal to 0.2 eV and also less than or equal to 2 eV,less than or equal to 1 eV, less than or equal to 0.5 eV, or less thanor equal to 0.4 eV. That is, the difference between the electronaffinity of the oxide semiconductor layer 122 and the electron affinityof each of the oxide insulating layers 121 and 123 is greater than orequal to 0.05 eV, greater than or equal to 0.07 eV, greater than orequal to 0.1 eV, or greater than or equal to 0.2 eV and also less thanor equal to 2 eV, less than or equal to 1 eV, less than or equal to 0.5eV, or less than or equal to 0.4 eV. Note that the electron affinityrefers to an energy difference between the vacuum level and theconduction band minimum.

When the oxide insulating layers 121 and 123 each contain a largeramount of Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, Hf, or Nd in an atomicratio than the amount of In in an atomic ratio, any of the followingeffects may be obtained.

-   (1) The energy gap of each of the oxide insulating layers 121 and    123 is widened.-   (2) The electron affinity of each of the oxide insulating layers 121    and 123 is reduced.-   (3) Impurities from the outside are blocked.-   (4) An insulating property of each of the oxide insulating layers    121 and 123 is higher than that of the oxide semiconductor layer    122.-   (5) Oxygen vacancies are less likely to be generated in the oxide    insulating layers 121 and 123 because Al, Ti, Ga, Y, Zr, Sn, La, Ce,    Mg, Hf, and Nd are metal elements that can be strongly bonded to    oxygen.

Since the oxide insulating layers 121 and 123 have higher insulatingproperties than the oxide semiconductor layer 122, they each have afunction of a gate insulating film.

In the case where the oxide insulating layers 121 and 123 are each anIn-M-Zn oxide, the proportion of In and the proportion of M, not takingZn and O into consideration, are less than 50 atomic % and greater thanor equal to 50 atomic %, respectively, and preferably less than 25atomic % and greater than or equal to 75 atomic %, respectively.

Further, in the case where the oxide insulating layers 121 and 123 areeach an In-M-Zn oxide (M is Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, Hf, orNd), the proportion ofM atoms (M is Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg,Hf, or Nd) in each of the oxide insulating layers 121 and 123 is higherthan that in the oxide semiconductor layer 122. Typically, theproportion of M in each of the oxide insulating layers 121 and 123 ishigher than or equal to 1.5 times, preferably higher than or equal totwice, further preferably higher than or equal to three times as high asthat in the oxide semiconductor layer 122. Any of the above-describedelements represented by M is more strongly bonded to oxygen than indiumis, and thus has a function of suppressing generation of oxygenvacancies in the oxide insulating layers 121 and 123. That is, oxygenvacancies are less likely to be generated in the oxide insulating layers121 and 123 than in the oxide semiconductor layer 122.

The indium content in the oxide semiconductor layer 122 is preferablyhigher than those in the oxide insulating layers 121 and 123. In anoxide semiconductor, an s orbital of heavy metal mainly contributes tocarrier transfer. When the proportion of In in the oxide semiconductoris increased, overlap of s orbitals is likely to be increased.Therefore, an oxide having a composition in which the proportion of Inis higher than that of M has higher mobility than an oxide having acomposition in which the proportion of In is equal to or lower than thatof M Thus, with the use of an oxide having a high content of indium forthe oxide semiconductor layer 122, a transistor having high field-effectmobility can be obtained.

In the case where the oxide semiconductor layer 122 contains an In-M-Znoxide (M is Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, Hf, or Nd) and a targethaving the atomic ratio of metal elements of In:M:Zn=x₁:y₁:z₁ is usedfor forming the oxide semiconductor layer 122, x₁/y₁ is preferablygreater than or equal to ⅓ and less than or equal to 6, furtherpreferably greater than or equal to 1 and less than or equal to 6, andz₁/y₁ is preferably greater than or equal to ⅓ and less than or equal to6, further preferably greater than or equal to 1 and less than or equalto 6. Note that when z₁/y₁ is greater than or equal to 1 and less thanor equal to 6, a c-axis aligned crystalline oxide semiconductor(CAAC-OS) film is easily formed as the oxide semiconductor layer 122.Typical examples of the atomic ratio of metal elements of the targetinclude In:M:Zn=1:1:1, 1:1:1.2, 2:1:1.5,2:1:2.3, 2:1:3, 3:1:2, 4:2:3,and 4:2:4.1.

The atomic ratio is not limited to those described above, and may beappropriately set in accordance with needed semiconductorcharacteristics.

In the case where the oxide insulating layers 121 and 123 contain anIn-M-Zn oxide (M is Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, Hf, or Nd) and atarget having the atomic ratio of metal elements of In:M:Zn=x₂:y₂:z₂ isused for forming the oxide insulating layers 121 and 123, x₂/y₂ ispreferably less than x₁/y₁, and z₂/y₂ is preferably greater than orequal to ⅓ and less than or equal to 6, further preferably greater thanor equal to 1 and less than or equal to 6. Note that when z₂/y₂ isgreater than or equal to 1 and less than or equal to 6, a CAAC-OS filmis easily formed as the oxide insulating layers 121 and 123. Typicalexamples of the atomic ratio of the metal elements of the target areIn:M:Zn=1:3:2, 1:3:4, 1:3:6, 1:3:8, 1:4:4, 1:4:5, 1:4:6, 1:4:7, 1:4:8,1:5:5, 1:5:6, 1:5:7, 1:5:8, 1:6:8, 1:6:4, and 1:9:6.

In each of the oxide insulating layers 121 and 123, the proportion ofeach atom in the above-described atomic ratio varies within a range of±40% as an error.

Alternatively, the oxide insulating layer 123 can be metal oxide, suchas aluminum oxide, gallium oxide, hafnium oxide, silicon oxide,germanium oxide, or zirconia oxide; or the metal oxide may be providedover the oxide insulating layer 123.

The oxide insulating layers 121 and 123 may have the same composition.For example, the oxide insulating layers 121 and 123 may contain anIn—Ga—Zn oxide with an atomic ratio of In:Ga:Zn=1:3:2, 1:3:4, or 1:4:5.

Alternatively, the oxide insulating layers 121 and 123 may havedifferent compositions. For example, the oxide insulating layer 121 andthe oxide insulating layer 123 may be formed using an In—Ga—Zn oxidewith an atomic ratio of In:Ga:Zn=1:3:4 and an In—Ga—Zn oxide with anatomic ratio of In:Ga:Zn=1:3:2, respectively, as targets used in asputtering method.

The thickness of each of the oxide insulating layer 121, the oxidesemiconductor layer 122, and the oxide insulating layer 123 ispreferably greater than or equal to 3 nm and less than or equal to 100nm or greater than or equal to 3 nm and less than or equal to 50 nm.

The thickness of the oxide semiconductor layer 122 may be greater than,equal to, or less than that of at least the oxide insulating layer 121.If the thickness of the oxide semiconductor layer 122 is greater thanthat of the oxide insulating layer 121, the on-state current of thetransistor can be increased. The thickness of the oxide insulating layer121 may be determined as appropriate as long as formation of aninterface state at the interface with the oxide semiconductor layer 122can be inhibited. For example, the thickness of the oxide semiconductorlayer 122 is greater than that of the oxide insulating layer 121,preferably 2 or more times, further preferably 4 or more times, stillfurther preferably 6 or more times as large as that of the oxideinsulating layer 121. In the case where there is no need to increase theon-state current of the transistor, the thickness of the oxideinsulating layer 121 may be greater than or equal to that of the oxidesemiconductor layer 122. If oxygen is added to the insulating layer 110or the insulating layer 175, oxygen vacancies in the oxide semiconductorlayer 122 can be reduced by heat treatment, which leads to stabilizationof electrical characteristics of the semiconductor device.

The thickness of the oxide insulating layer 123 may be determined asappropriate, in a manner similar to that of the oxide insulating layer121, as long as formation of an interface state at the interface withthe oxide semiconductor layer 122 is inhibited. For example, thethickness of the oxide insulating layer 123 may be set less than orequal to that of the oxide insulating layer 121. If the thickness of theoxide insulating layer 123 is large, there is a concern that theelectric field from the gate electrode layer 160 (or the gate electrodelayer 161 and the gate electrode layer 162) cannot reach the oxidesemiconductor layer 122. For this reason, the thickness of the oxideinsulating layer 123 is preferably small. To prevent oxygen contained inthe oxide insulating layer 123 from diffusing to the source and drainelectrode layers 130 and 140 and oxidizing the source and drainelectrode layers 130 and 140, it is preferable that the thickness of theoxide insulating layer 123 be small. For example, the thickness of theoxide insulating layer 123 is less than that of the oxide semiconductorlayer 122. Note that the thickness of the oxide insulating layer 123 isnot limited to the above, and may be determined as appropriate inaccordance with the driving voltage of the transistor in considerationof the withstand voltage of the gate insulating layer 150.

In the case where the oxide insulating layer 121, the oxidesemiconductor layer 122, and the oxide insulating layer 123 havedifferent compositions from one another, the interfaces thereof can beobserved by scanning transmission electron microscopy (STEM).

<Hydrogen Concentration>

Hydrogen contained in the oxide insulating layer 121, the oxidesemiconductor layer 122, and the oxide insulating layer 123 reacts withoxygen bonded to a metal atom to be water, and in addition, an oxygenvacancy is formed in a lattice from which oxygen is released (or aportion from which oxygen is released). An electron serving as a carriercan be generated due to entry of hydrogen into the oxygen vacancy or dueto bonding of part of hydrogen to oxygen bonded to a metal element.Thus, a transistor including an oxide semiconductor which containshydrogen is likely to be normally on.

Accordingly, it is preferable that hydrogen be reduced as much aspossible as well as the oxygen vacancies in the oxide insulating layer121, the oxide semiconductor layer 122, and the oxide insulating layer123 and at the interfaces between the oxide insulating layer 121, theoxide semiconductor layer 122, and the oxide insulating layer 123. Theconcentrations of hydrogen in the oxide insulating layer 121, the oxidesemiconductor layer 122, and the oxide insulating layer 123 and at theinterfaces between the oxide insulating layer 121, the oxidesemiconductor layer 122, and the oxide insulating layer 123, which areobtained by secondary ion mass spectrometry (SIMS), are desirably higherthan or equal to 1×10¹⁶ atoms/cm³ and lower than or equal to 2×10²⁰atoms/cm³, preferably higher than or equal to 1×10¹⁶ atoms/cm³ and lowerthan or equal to 5×10¹⁹ atoms/cm³, further preferably higher than orequal to 1×10¹⁶ atoms/cm³ and lower than or equal to 1×10¹⁹ atoms/cm³,still further preferably higher than or equal to 1×10¹⁶ atoms/cm³ andlower than or equal to 5×10¹⁸ atoms/cm³. As a result, the transistor 10can have positive threshold voltage (normally-off characteristics).

<Concentrations of Carbon and Silicon>

When silicon and carbon, which are elements belonging to Group 14, arecontained in the oxide insulating layer 121, the oxide semiconductorlayer 122, and the oxide insulating layer 123 and at the interfacesbetween the oxide insulating layer 121, the oxide semiconductor layer122, and the oxide insulating layer 123, oxygen vacancies are increasedand an n-type region is formed in the oxide insulating layer 121, theoxide semiconductor layer 122, and the oxide insulating layer 123. It istherefore preferable to reduce the concentrations of silicon and carbonin the oxide insulating layer 121, the oxide semiconductor layer 122,and the oxide insulating layer 123 and at the interfaces between theoxide insulating layer 121, the oxide semiconductor layer 122, and theoxide insulating layer 123. The concentrations of silicon and carbon inthe oxide insulating layer 121, the oxide semiconductor layer 122, andthe oxide insulating layer 123 and at the interfaces between the oxideinsulating layer 121, the oxide semiconductor layer 122, and the oxideinsulating layer 123, which are obtained by SIMS, are desirably higherthan or equal to 1×10¹⁶ atoms/cm³ and lower than or equal to1×10^(19 atoms/cm) ³, further preferably higher than or equal to 1×10¹⁶atoms/cm³ and lower than or equal to 5×10¹⁸ atoms/cm³, still furtherpreferably higher than or equal to 1×10¹⁶ atoms/cm³ and lower than orequal to 2×10¹⁸ atoms/cm³. As a result, the transistor 10 can havepositive threshold voltage (normally-off characteristics).

<Concentration of Alkali Metal>

Alkali metal and alkaline earth metal can generate carriers when bondedto an oxide semiconductor, which can increase the off-state current ofthe transistor. It is thus preferable to reduce the concentrations ofalkali metal and alkaline earth metal in the oxide insulating layer 121,the oxide semiconductor layer 122, and the oxide insulating layer 123and at the interfaces between the oxide insulating layer 121, the oxidesemiconductor layer 122, and the oxide insulating layer 123. Forexample, the concentrations of alkali metal and alkaline earth metal inthe oxide insulating layer 121, the oxide semiconductor layer 122, andthe oxide insulating layer 123 and at the interfaces between the oxideinsulating layer 121, the oxide semiconductor layer 122, and the oxideinsulating layer 123, which are obtained by SIMS, are preferably lowerthan or equal to 1×10¹⁸ atoms/cm³, more preferably lower than or equalto 2×10¹⁶ atoms/cm³. As a result, the transistor 10 can have positivethreshold voltage (normally-off characteristics).

<Concentration of Nitrogen>

When nitrogen is contained in the oxide insulating layer 121, the oxidesemiconductor layer 122, and the oxide insulating layer 123 and at theinterfaces between the oxide insulating layer 121, the oxidesemiconductor layer 122, and the oxide insulating layer 123, an electronserving as a carrier is generated and accordingly carrier density isincreased, so that n-type regions are formed. Thus, when an oxidesemiconductor contains nitrogen, a transistor including the oxidesemiconductor is likely to be normally on. Thus, it is preferable thatnitrogen be reduced as much as possible in the oxide insulating layer121, the oxide semiconductor layer 122, and the oxide insulating layer123 and at the interfaces between the oxide insulating layer 121, theoxide semiconductor layer 122, and the oxide insulating layer 123. Forexample, the concentrations of nitrogen in the oxide insulating layer121, the oxide semiconductor layer 122, and the oxide insulating layer123 and at the interfaces between the oxide insulating layer 121, theoxide semiconductor layer 122, and the oxide insulating layer 123, whichare obtained by SIMS, are preferably higher than or equal to 1×10¹⁵atoms/cm³ and lower than or equal to 5×10¹⁹ atoms/cm³, furtherpreferably higher than or equal to 1×10¹⁵ atoms/cm³ and lower than orequal to 5×10¹⁸ atoms/cm³, still further preferably higher than or equalto 1×10¹⁵ atoms/cm³ and lower than or equal to 1×10¹⁸ atoms/cm³, stillfurther preferably higher than or equal to 1×10¹⁵ atoms/cm³ and lowerthan or equal to 5×10¹⁷ atoms/cm³. As a result, the transistor 10 canhave positive threshold voltage (normally-off characteristics).

However, in the case where excess zinc exists in the oxide semiconductorlayer 122, the concentrations of nitrogen are not limited to the aboverange. To improve the crystallinity of the oxide semiconductor layer122, it is effective to increase the content of zinc. However, excesszinc might cause shallow density of defect states (sDOS) in the oxidesemiconductor layer 122. In order to increase the content of zinc andreduce the sDOS, the oxide semiconductor layer 122 contains nitrogen at0.001 atomic % to 3 atomic % because the sDOS caused by excess zinc canbe inactivated in some cases. Therefore, the nitrogen can reducevariations in transistor characteristics and can improve thereliability.

<Carrier Density>

The carrier densities of the oxide insulating layer 121, the oxidesemiconductor layer 122, and the oxide insulating layer 123 can belowered by reduction in impurities in the oxide insulating layer 121,the oxide semiconductor layer 122, and the oxide insulating layer 123.The carrier densities of the oxide insulating layer 121, the oxidesemiconductor layer 122, and the oxide insulating layer 123 is1×10¹⁵/cm³ or less, preferably 1×10¹³/cm³ or less, further preferablyless than 8×10¹¹/cm³, still further preferably less than 1×10¹¹/cm³, andyet still further preferably less than 1×10¹⁰/cm³ and 1×10⁻⁹/cm³ ormore.

When an oxide film having a low impurity concentration and a low densityof defect states is used as each of the oxide insulating layer 121, theoxide semiconductor layer 122, and the oxide insulating layer 123, atransistor including the oxide semiconductor layers can have moreexcellent electrical characteristics. Here, the state in which theimpurity concentration is low and the density of defect states is low(the amount of oxygen vacancies is small) is described as “highlypurified intrinsic” or “substantially highly purified intrinsic.” Ahighly purified intrinsic or substantially highly purified intrinsicoxide semiconductor has few carrier generation sources, and thus has alow carrier density in some cases. Thus, a transistor including theoxide semiconductor film in which a channel region is formed is likelyto have positive threshold voltage (normally-off characteristics). Ahighly purified intrinsic or substantially highly purified intrinsicoxide semiconductor film has a low density of defect states andaccordingly has a low density of trap states in some cases. Further, ahighly purified intrinsic or substantially highly purified intrinsicoxide semiconductor film has an extremely low off-state current; theoff-state current can be less than or equal to the measurement limit ofa semiconductor parameter analyzer, i.e., less than or equal to1×10^(—13) A, at a voltage between a source electrode and a drainelectrode (drain voltage) of from 1 V to 10 V. Thus, the transistorwhose channel region is formed in the oxide semiconductor film has asmall variation in electrical characteristics and high reliability insome cases.

A transistor in which a highly purified oxide semiconductor film is usedfor a channel formation region exhibits extremely low off-state current.For example, in the case where the voltage between the source and thedrain is set to approximately 0.1 V, 5 V, or 10 V, the off-state currentstandardized on the channel width of the transistor can be as low asseveral yoctoamperes per micrometer to several zeptoamperes permicrometer.

The oxide insulating layer 121, the oxide semiconductor layer 122, andthe oxide insulating layer 123 may have a non-single crystal structure,for example. The non-single crystal structure includes a CAAC-OS whichis described later, a polycrystalline structure, a microcrystallinestructure, or an amorphous structure, for example. Among the non-singlecrystal structure, the amorphous structure has the highest density ofdefect states, whereas the CAAC-OS has the lowest density of defectstates.

The oxide insulating layer 121, the oxide semiconductor layer 122, andthe oxide insulating layer 123 may have a microcrystalline structure,for example. The oxide insulating layer 121, the oxide semiconductorlayer 122, and the oxide insulating layer 123 which have themicrocrystalline structure each include a microcrystal with a sizegreater than or equal to 1 nm and less than 10 nm, for example.Alternatively, the oxide semiconductor films which have themicrocrystalline structure have a mixed phase structure where crystalparts (each of which is greater than or equal to 1 nm and less than 10nm) are distributed in an amorphous phase.

The oxide insulating layer 121, the oxide semiconductor layer 122, andthe oxide insulating layer 123 may have an amorphous structure, forexample. The oxide insulating layer 121, the oxide semiconductor layer122, and the oxide insulating layer 123 which have the amorphousstructure each have disordered atomic arrangement and no crystallinecomponent, for example. Alternatively, the oxide semiconductor filmswhich have an amorphous structure have, for example, an absolutelyamorphous structure and no crystal part.

Note that the oxide insulating layer 121, the oxide semiconductor layer122, and the oxide insulating layer 123 may each be a mixed filmincluding regions having two or more of the following structures: aCAAC-OS, a microcrystalline structure, and an amorphous structure. Themixed film, for example, has a single-layer structure including a regionhaving an amorphous structure, a region having a microcrystallinestructure, and a region of a CAAC-OS. Alternatively, the mixed film mayhave a stacked-layer structure including a region having an amorphousstructure, a region having a microcrystalline structure, and a region ofa CAAC-OS, for example.

Note that the oxide insulating layer 121, the oxide semiconductor layer122, and the oxide insulating layer 123 may have a single-crystalstructure, for example.

By providing an oxide film in which oxygen vacancies are less likely tobe generated than in the oxide semiconductor layer 122, over and underand in contact with the oxide semiconductor layer 122, oxygen vacanciesin the oxide semiconductor layer 122 can be reduced. Further, since theoxide semiconductor layer 122 is in contact with the oxide insulatinglayers 121 and 123 containing one or more metal elements forming theoxide semiconductor layer 122, the density of interface states at theinterface between the oxide insulating layer 121 and the oxidesemiconductor layer 122 and at the interface between the oxidesemiconductor layer 122 and the oxide insulating layer 123 is extremelylow. For example, after oxygen is added to the oxide insulating layer121, the oxide insulating layer 123, the gate insulating layer 150, theinsulating layer 110, and the insulating layer 175, the oxygen istransferred through the oxide insulating layers 121 and 123 to the oxidesemiconductor layer 122 by heat treatment; however, the oxygen is hardlytrapped by the interface states at this time, and the oxygen in theoxide insulating layers 121 and 123 can be efficiently transferred tothe oxide semiconductor layer 122. Accordingly, oxygen vacancies in theoxide semiconductor layer 122 can be reduced. Since oxygen is added tothe oxide insulating layers 121 and 123, oxygen vacancies in the oxideinsulating layers 121 and 123 can be reduced. In other words, thedensity of localized states of at least the oxide semiconductor layer122 can be reduced.

In addition, when the oxide semiconductor layer 122 is in contact withan insulating film including a different constituent element (e.g., agate insulating film including a silicon oxide film), an interface stateis sometimes formed and the interface state forms a channel. At thistime, a second transistor having a different threshold voltage appears,so that an apparent threshold voltage of the transistor is varied.However, since the oxide insulating layers 121 and 123 containing one ormore kinds of metal elements forming the oxide semiconductor layer 122are in contact with the oxide semiconductor layer 122, an interfacestate is not easily formed at the interfaces between the oxideinsulating layer 121 and the oxide semiconductor layer 122 and betweenthe oxide insulating layer 123 and the oxide semiconductor layer 122.

The oxide insulating layers 121 and 123 function as barrier films thatprevent constituent elements of the insulating layer 110 and the gateinsulating layer 150 from entering the oxide semiconductor layer 122 andforming an impurity state.

For example, in the case of using a silicon-containing insulating filmas the insulating layer 110 or the gate insulating layer 150, silicon inthe gate insulating layer 150 or carbon which might be contained in theinsulating layer 110 or the gate insulating layer 150 enters the oxideinsulating layer 121 or 123 to a depth of several nanometers from theinterface in some cases. An impurity, such as silicon or carbon,entering the oxide semiconductor layer 122 forms an impurity state. Theimpurity state serves as a donor to generate an electron; thus, ann-type semiconductor might be formed.

However, when each thickness of the oxide insulating layers 121 and 123is larger than several nanometers, the impurity such as silicon orcarbon does not reach the oxide semiconductor layer 122, so that theinfluence of impurity states is reduced.

Thus, providing the oxide insulating layers 121 and 123 makes itpossible to reduce variations in electrical characteristics of thetransistor, such as threshold voltage.

In the case where the gate insulating layer 150 and the oxidesemiconductor layer 122 are in contact with each other and a channel isformed at interfaces therebetween, interface scattering occurs at theinterfaces and the field-effect mobility of the transistor is decreased.However, since the oxide insulating layers 121 and 123 containing one ormore kinds of metal elements forming the oxide semiconductor layer 122are provided in contact with the oxide semiconductor layer 122,scattering of carriers does not easily occur at the interfaces betweenthe oxide semiconductor layer 122 and each of the oxide insulatinglayers 121 and 123, and thus the field-effect mobility of the transistorcan be increased.

In this embodiment, the amount of oxygen vacancies in the oxidesemiconductor layer 122, and further the amount of oxygen vacancies inthe oxide insulating layers 121 and 123 in contact with the oxidesemiconductor layer 122 can be reduced; thus, the density of localizedstates of the oxide semiconductor layer 122 can be reduced. As a result,the transistor 10 in this embodiment has small variations in thresholdvoltage and high reliability. Further, the transistor 10 of thisembodiment has excellent electrical characteristics.

An insulating film containing silicon is often used as a gate insulatinglayer of a transistor. For the above-described reason, it is preferablethat a region of the oxide semiconductor layer, which serves as achannel, be not in contact with the gate insulating layer as in thetransistor of one embodiment of the present invention. In the case wherea channel is formed at the interface between the gate insulating layerand the oxide semiconductor layer, scattering of carriers occurs at theinterface, whereby the field-effect mobility of the transistor isreduced in some cases. Also from the view of the above, it is preferablethat the region of the oxide semiconductor layer, which serves as achannel, be separated from the gate insulating layer.

Accordingly, with the oxide semiconductor layer 120 having astacked-layer structure including the oxide insulating layer 121, theoxide semiconductor layer 122, and the oxide insulating layer 123, achannel can be formed in the oxide semiconductor layer 122; thus, thetransistor can have a high field-effect mobility and stable electricalcharacteristics.

Note that the three oxide layers are not necessarily provided and can bea single layer, two layers, four layers, or five or more layers. In thecase of a single layer, a layer corresponding to the oxide semiconductorlayer 122, which is described in this embodiment, can be used.

<Band Diagram>

Here, a band diagram is described. For easy understanding, the banddiagram is illustrated with the energy levels (Ec) at the conductionband minimum of the insulating layer 110, the oxide insulating layer121, the oxide semiconductor layer 122, the oxide insulating layer 123,and the gate insulating layer 150.

As illustrated in FIGS. 3A and 3B, the energy at the conduction bandminimum changes continuously within the oxide insulating layer 121, theoxide semiconductor layer 122, and the oxide insulating layer 123. Thiscan be understood also from the fact that the constituent elements arecommon among the oxide insulating layer 121, the oxide semiconductorlayer 122, and the oxide insulating layer 123 and oxygen is easilydiffused among them. Thus, the oxide insulating layer 121, the oxidesemiconductor layer 122, and the oxide insulating layer 123 have acontinuous physical property although they are a stack of films havingdifferent compositions.

The oxide semiconductor films, which contain the same main componentsand are stacked, are not simply stacked but formed to have continuousjunction (here, particularly a U-shaped (U shape) well structure wherethe energy at the conduction band minimum is continuously changedbetween the films). In other words, a stacked-layer structure is formedsuch that there exists no impurities which form a defect level such as atrap center or a recombination center at each interface. If impuritiesare mixed between the films in the stacked multilayer film, thecontinuity of the energy band is lost and carriers disappear by a trapor recombination at the interface.

Although Ec of the oxide insulating layer 121 and the oxide insulatinglayer 123 are equal to each other in FIG. 3B, they may be different.

As illustrated in FIG. 3B, the oxide semiconductor layer 122 serves as awell and a channel of the transistor 10 is formed in the oxidesemiconductor layer 122. Note that a channel having a U-shaped wellstructure in which the energy at the conduction band minimumcontinuously changes like the one formed in the oxide semiconductorlayer 122, can also be referred to as a buried channel.

Note that trap levels due to impurities or defects can be formed in thevicinity of the interface between an insulating film such as a siliconoxide film and the oxide insulating layers 121 and 123. The oxidesemiconductor layer 122 can be distanced away from the trap levels owingto existence of the oxide insulating layers 121 and 123. However, whenthe energy difference between Ec of the oxide insulating layers 121 and123 and Ec of the oxide semiconductor layer 122 is small, an electron inthe oxide semiconductor layer 122 can go over the energy difference andreach the trap level. When electrons to be negative charge are capturedby the trap levels, a negative fixed charge is generated at theinterface with the insulating film, whereby the threshold voltage of thetransistor is shifted in the positive direction. In addition, a trap isnot fixed and characteristics can be changed in a long-time preservationtest of a transistor.

Thus, to reduce a change in the threshold voltage of the transistor, anenergy difference between the Ec of the oxide semiconductor layer 122and the Ec of each of the oxide insulating layers 121 and 123 isnecessary. The energy difference is preferably greater than or equal to0.1 eV, further preferably greater than or equal to 0.2 eV.

The oxide insulating layer 121, the oxide semiconductor layer 122, andthe oxide insulating layer 123 preferably include a crystal. Inparticular, when a crystal in which c-axes are aligned is used, thetransistor can have stable electrical characteristics.

In the band diagram illustrated in FIG. 3B, In—Ga oxide (e.g., with anatomic ratio of In: Ga=7:93) or gallium oxide may be provided betweenthe oxide semiconductor layer 122 and the gate insulating layer 150without providing the oxide insulating layer 123. Furthermore, In—Gaoxide or gallium oxide may be provided between the oxide insulatinglayer 123 and the gate insulating layer 150.

As the oxide semiconductor layer 122, an oxide having an electronaffinity higher than those of the oxide insulating layers 121 and 123 isused. The oxide which can be used for the oxide semiconductor layer 122has, for example, an electron affinity higher than that of each of theoxide insulating layers 121 and 123 by 0.07 eV or higher and 1.3 eV orlower, preferably 0.1 eV or higher and 0.7 eV or lower, and furtherpreferably 0.2 eV or higher and 0.4 eV or lower.

Since the transistor described in this embodiment includes the oxideinsulating layers 121 and 123 that each include one or more kinds ofmetal elements included in the oxide semiconductor layer 122, aninterface state is less likely to formed at the interface between theoxide insulating layer 121 and the oxide semiconductor layer 122 and theinterface between the oxide insulating layer 123 and the oxidesemiconductor layer 122. Thus, providing the oxide insulating layers 121and 123 makes it possible to reduce variations or changes in electricalcharacteristics of the transistor, such as threshold voltage.

<<Source Electrode Layer 130 and Drain Electrode Layer 140>>

The source electrode layer 130 and the drain electrode layer 140 arepreferably a conductive layer having a single-layer structure or astacked-layer structure and containing a material selected from copper(Cu), tungsten (W), molybdenum (Mo), gold (Au), aluminum (Al), manganese(Mn), titanium (Ti), tantalum (Ta), nickel (Ni), chromium (Cr), lead(Pb), tin (Sn), iron (Fe), cobalt (Co), ruthenium (Ru), platinum (Pt),iridium (Ir), and strontium (Sr), an alloy of such a material, or acompound of oxygen, nitrogen, fluorine, or silicon containing any ofthese materials as its main component. For example, in the case ofstacking layers, the lower conductive layer which is in contact with theoxide semiconductor layer 122 contains a material which is easilycombined with oxygen, and the upper conductive layer contains a highlyoxidation-resistant material. It is preferable to use ahigh-melting-point material, such as tungsten or molybdenum, which hasboth heat resistance and conductivity. In addition, the conductive layeris preferably formed using a low-resistance conductive material such asaluminum or copper. The conductive layer is further preferably formedusing a Cu—Mn alloy, since in that case, manganese oxide formed at theinterface with an insulator containing oxygen has a function ofsuppressing Cu diffusion.

When the conductive material that is easily bonded to oxygen is incontact with an oxide semiconductor layer, a phenomenon occurs in whichoxygen in the oxide semiconductor layer is diffused to the conductivematerial that is easily bonded to oxygen. Oxygen vacancies are generatedin the vicinity of a region which is in the oxide semiconductor layerand is in contact with the source electrode layer or the drain electrodelayer. Hydrogen slightly contained in the film enters the oxygenvacancies, whereby the region is markedly changed to an n-type region.Accordingly, the n-type region can serve as a source or a drain of thetransistor.

For example, a stacked-layer structure using W and Pt for the lowerconductive layer and the upper conductive layer, respectively, cansuppress oxidation of the conductive layers caused by being in contactwith the insulating layer 175 while an oxide semiconductor in contactwith the conductive layers becomes n-type.

<<Gate Insulating Layer 150>>

The gate insulating layer 150 can contain oxygen, nitrogen, fluorine,aluminum, magnesium, silicon, gallium, germanium, yttrium, zirconium,lanthanum, neodymium, hafnium, tantalum, titanium, or the like. Forexample, an insulating film containing one or more of aluminum oxide,magnesium oxide, silicon oxide, silicon oxynitride, silicon nitrideoxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide,zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, andtantalum oxide can be used. The gate insulating layer 150 may be a stackof any of the above materials. The gate insulating layer 150 may containlanthanum (La), nitrogen, zirconium (Zr), or the like as an impurity.

An example of a stacked-layer structure of the gate insulating layer 150will be described. The gate insulating layer 150 contains, for example,oxygen, nitrogen, silicon, or hafnium. Specifically, the gate insulatinglayer 150 preferably contains hafnium oxide and silicon oxide or siliconoxynitride.

Hafnium oxide has higher dielectric constant than silicon oxide andsilicon oxynitride. Therefore, by using hafnium oxide, the thickness ofthe gate insulating layer 150 can be larger than that of silicon oxide;thus, leakage current due to tunnel current can be low. That is, it ispossible to provide a transistor with a low off-state current. Moreover,hafnium oxide with a crystalline structure has higher dielectricconstant than hafnium oxide with an amorphous structure. Therefore, itis preferable to use hafnium oxide with a crystalline structure in orderto provide a transistor with a low off-state current. Examples of thecrystalline structure include a monoclinic crystal structure and a cubiccrystal structure. Note that one embodiment of the present invention isnot limited to the above examples.

In some cases, an interface state due to a defect exists in hafniumoxide having a crystalline structure in a formation surface where thehafnium oxide having the crystalline structure is formed. The interfacestate serves as a trap center in some cases. Therefore, when hafniumoxide is provided near a channel region of a transistor, the electricalcharacteristics of the transistor might deteriorate because of theinterface state. In order to reduce the adverse effect of the interfacestate, in some cases, it is preferable to separate the channel region ofthe transistor and the hafnium oxide from each other by providinganother film therebetween. The film has a buffer function. The filmhaving a buffer function may be included in the gate insulating layer150 or included in the oxide semiconductor film. That is, the filmhaving a buffer function can be formed using silicon oxide, siliconoxynitride, an oxide semiconductor, or the like. Note that the filmhaving a buffer function is formed using, for example, a semiconductoror an insulator having a larger energy gap than a semiconductor to bethe channel region. Alternatively, the film having a buffer function isformed using, for example, a semiconductor or an insulator having lowerelectron affinity than a semiconductor to be the channel region. Furtheralternatively, the film having a buffer function is formed using, forexample, a semiconductor or an insulator having higher ionization energythan a semiconductor to be the channel region.

In some cases, the threshold voltage of a transistor can be controlledby trapping an electric charge in an interface state (trap center) inhafnium oxide having the above-described crystalline structure in theformation surface where the hafnium oxide having the above-describedcrystalline structure is formed. In order to make the electric chargeexist stably, for example, an insulator having a larger energy gap thanhafnium oxide may be provided between the channel region and the hafniumoxide. Alternatively, a semiconductor or an insulator having lowerelectron affinity than hafnium oxide may be provided. The film having abuffer function may be formed using a semiconductor or an insulatorhaving higher ionization energy than hafnium oxide. With the use of suchan insulator, an electric charge trapped in the interface state is lesslikely to be released; accordingly, the electric charge can be held fora long period of time.

Examples of such an insulator include silicon oxide and siliconoxynitride. In order to make the interface state in the gate insulatinglayer 150 trap an electric charge, an electron may be transferred froman oxide semiconductor film toward the gate electrode layer 160. As aspecific example, the potential of the gate electrode layer 160 is kepthigher than the potential of the source electrode layer 130 or the drainelectrode layer 140 under high temperature conditions (e.g., atemperature higher than or equal to 125° C. and lower than or equal to450° C., typically higher than or equal to 150° C. and lower than orequal to 300° C.) for one second or longer, typically for one minute orlonger.

The threshold voltage of a transistor in which a predetermined amount ofelectrons are trapped in interface states in the gate insulating layer150 or the like shifts in the positive direction. The amount ofelectrons to be trapped (the amount of change in threshold voltage) canbe controlled by adjusting a voltage of the gate electrode layer 160 ortime in which the voltage is applied. Note that a location in which anelectric charge is trapped is not necessarily limited to the inside ofthe gate insulating layer 150 as long as an electric charge can betrapped therein. A stacked film having a similar structure may be usedas another insulating layer.

<<Gate Electrode Layer 160>>

The gate electrode layer 160 can be formed using aluminum (Al), titanium(Ti), chromium (Cr), cobalt (Co), nickel (Ni), copper (Cu), yttrium (Y),zirconium (Zr), molybdenum (Mo), ruthenium (Ru), silver (Ag), tantalum(Ta), tungsten (W), or silicon (Si), for example. The gate electrodelayer 160 may have a stacked-layer structure. Any of these materials maybe used for the gate electrode layer 162. A conductive film containingnitrogen, such as a nitride of any of the above materials, may be usedfor the gate electrode layer 161. For the gate electrode layer 160, anoxide having conductivity may be used.

<<Insulating Layer 170>>

The insulating layer 170 can contain at least one of aluminum oxide,magnesium oxide, silicon oxide, silicon oxynitride, silicon nitrideoxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide,zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, andtantalum oxide.

An aluminum oxide film is preferably included in the insulating layer170. The aluminum oxide film can prevent the passage of both oxygen andimpurities such as hydrogen and moisture. Thus, during and after themanufacturing process of the transistor, the aluminum oxide film cansuitably function as a protective film that has effects of preventingentry of impurities such as hydrogen and moisture, which causevariations in the electrical characteristics of the transistor, into theoxide insulating layer 121, the oxide semiconductor layer 122, and theoxide insulating layer 123, preventing release of oxygen, which is amain component, from the oxide insulating layer 121, the oxidesemiconductor layer 122, and the oxide insulating layer 123, andpreventing unnecessary release of oxygen from the insulating layer 110.

The insulating layer 170 is preferably a film having oxygen supplycapability. Oxygen is supplied to other oxide layers when the insulatinglayer 170 is formed, the oxygen is diffused into an oxide semiconductorby heat treatment performed after that, and the oxygen can be suppliedto oxygen vacancies in the oxide semiconductor; therefore, thetransistor characteristics (e.g., threshold voltage and reliability) canbe improved.

Further, the insulating layer 170 may be a single layer or a stackedlayer. Alternatively, another insulating layer may be provided over orunder the insulating layer 170. The insulating layer 170 can be formedusing an insulating film containing one or more of magnesium oxide,silicon oxide, silicon oxynitride, silicon nitride oxide, siliconnitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide,lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, forexample. The insulating layer 170 preferably contains oxygen more thanthat in the stoichiometric composition. Oxygen released from theinsulating layer 170 can be diffused into the channel formation regionin the oxide semiconductor layer 120 through the gate insulating layer150, so that oxygen vacancies formed in the channel formation region canbe filled with the oxygen. In this manner, stable electricalcharacteristics of the transistor can be achieved.

<<Insulating Layer 175>>

The insulating layer 175 can be formed using an insulating filmcontaining one or more of magnesium oxide (MgO_(x)), silicon oxide(SiO_(x)), silicon oxynitride (SiN_(x)O_(x)), silicon nitride oxide(SiN_(x)O_(x)), silicon nitride (SiN_(x)), gallium oxide (GaO_(x)),germanium oxide (GeO_(x)), yttrium oxide (YO_(x)), zirconium oxide(ZrO_(x)), lanthanum oxide (RaO_(x)), neodymium oxide (NdO_(x)), hafniumoxide (HfO_(x)), tantalum oxide (TaO_(x)), and aluminum oxide (AlO_(x)).The insulating layer 175 may be a stack of any of the above materials.The insulating layer 175 preferably contains oxygen more than that inthe stoichiometric composition. Oxygen released from the insulatinglayer 175 can be diffused into the channel formation region in the oxidesemiconductor layer 120 through the gate insulating layer 150, so thatoxygen vacancies formed in the channel formation region can be filledwith the oxygen. In this manner, stable electrical characteristics ofthe transistor can be achieved.

<Manufacturing Method of Transistor>

Next, a manufacturing method of a semiconductor device of thisembodiment is described with reference to FIGS. 6A and 6B, FIGS. 7A and7B, FIGS. 8A and 8B, FIGS. 9A and 9B, FIGS. 10A and 10B, FIGS. 11A and11B, and FIGS. 12A and 12B. Note that the same parts as those in theabove transistor structure are not described here. The direction ofA1-A2 and that of A3-A4 in FIGS. 6A and 6B, FIGS. 7A and 7B, FIGS. 8Aand 8B, FIGS. 9A and 9B, FIGS. 10A and 10B, FIGS. 11A and 11B, and FIGS.12A and 12B are respectively referred to as a channel length directionand a channel width direction in FIGS. 1A and 1B in some cases.

In this embodiment, the layers included in the transistor (i.e., theinsulating layer, the oxide semiconductor layer, the conductive layer,and the like) can be formed by any of a sputtering method, a chemicalvapor deposition (CVD) method, a vacuum evaporation method, and a pulsedlaser deposition (PLD) method. Alternatively, a coating method or aprinting method can be used. Although the sputtering method and aplasma-enhanced chemical vapor deposition (PECVD) method are typicalexamples of the film formation method, a thermal CVD method may be used.As the thermal CVD method, a metal organic chemical vapor deposition(MOCVD) method or an atomic layer deposition (ALD) method may be used,for example. As the sputtering method, a combination of a long throwsputtering method and a collimated sputtering method is employed,whereby the embeddability can be improved.

<Thermal CVD Method>

A thermal CVD method has an advantage that no defect due to plasmadamage is generated since it does not utilize plasma for forming a film.

Deposition by a thermal CVD method may be performed in such a mannerthat a source gas and an oxidizer are supplied to the chamber at a time,the pressure in a chamber is set to an atmospheric pressure or a reducedpressure, and reaction is caused in the vicinity of the substrate orover the substrate.

The variety of films such as the metal film, the semiconductor film, andthe inorganic insulating film which have been disclosed in the aboveembodiments can be formed by a thermal

CVD method, such as a MOCVD method or an ALD method. For example, in thecase where an In—Ga—Zn—O film is formed, trimethylindium,trimethylgallium, and dimethylzinc can be used. Note that the chemicalformula of trimethylindium is In(CH₃)₃. The chemical formula oftrimethylgallium is Ga(CH₃)₃. The chemical formula of dimethylzinc isZn(CH₃)₂. Without limitation to the above combination, triethylgallium(chemical formula: Ga(C₂H₅)₃) can be used instead of trimethylgallium,and diethylzinc (chemical formula: Zn(C₂H₅)₂) can be used instead ofdimethylzinc.

<ALD Method>

In a conventional deposition apparatus utilizing a CVD method, one ormore kinds of source gases (precursors) for reaction are supplied to achamber at the same time at the time of deposition. In a depositionapparatus utilizing an ALD method, precursors for reaction aresequentially introduced into a chamber, and then the sequence of the gasintroduction is repeated. For example, two or more kinds of precursorsare sequentially supplied to the chamber by switching respectiveswitching valves (also referred to as high-speed valves). For example, afirst precursor is introduced, an inert gas (e.g., argon or nitrogen) orthe like is introduced after the introduction of the first precursor sothat the plural kinds of precursors are not mixed, and then a secondprecursor is introduced. Alternatively, the first precursor may beexhausted by vacuum evacuation instead of the introduction of the inertgas, and then the second precursor may be introduced.

FIGS. 4A to 4D illustrate a deposition process by an ALD method. Firstprecursors 601 are adsorbed onto a substrate surface (see FIG. 4A),whereby a first monolayer is formed (see FIG. 4B). At this time, metalatoms and the like included in the precursors can be bonded to hydroxylgroups that exist at the substrate surface. The metal atoms may bebonded to alkyl groups such as methyl groups or ethyl groups. The firstmonolayer reacts with second precursors 602 introduced after the firstprecursors 601 are evacuated (see FIG. 4C), whereby a second monolayeris stacked over the first monolayer. Thus, a thin film is formed (seeFIG. 4D). For example, in the case where an oxidizer is included in thesecond precursors, the oxidizer chemically reacts with metal atomsincluded in the first precursors or an alkyl group bonded to metalatoms, whereby an oxide film can be formed.

An ALD method is a deposition method based on a surface chemicalreaction, by which precursors are adsorbed onto a surface and adsorbingis stopped by a self-terminating mechanism, whereby a layer is formed.For example, precursors such as trimethylaluminum react with hydroxylgroups (OH groups) that exist at the surface. At this time, only asurface reaction due to heating occurs; therefore, the precursors comeinto contact with the surface and metal atoms or the like in theprecursors can be adsorbed onto the surface through thermal energy. Theprecursors have characteristics of, for example, having a high vaporpressure, being thermally stable before being deposited and notdissolving, and being chemically adsorbed onto a substrate at a highspeed. Since the precursors are introduced in a state of a gas, when theprecursors, which are alternately introduced, have enough time to bediffused, a film can be formed with good coverage even onto a regionhaving unevenness with a high aspect ratio.

In an ALD method, the sequence of the gas introduction is repeated aplurality of times until a desired thickness is obtained, whereby a thinfilm with excellent step coverage can be formed. The thickness of thethin film can be adjusted by the number of repetition times of thesequence of the gas introduction; therefore, an ALD method makes itpossible to accurately adjust a thickness. The deposition rate can beincreased and the impurity concentration in the film can be reduced byimproving the evacuation capability.

ALD methods include an ALD method using heating (thermal ALD method) andan ALD method using plasma (plasma ALD method). In the thermal ALDmethod, precursors react using thermal energy, and in the plasma ALDmethod, precursors react in a state of a radical.

By an ALD method, an extremely thin film can be formed with highaccuracy. In addition, the coverage of an uneven surface with the filmand the film density of the film are high.

<Plasma ALD>

Alternatively, when the plasma ALD method is employed, the film can beformed at a lower temperature than when the thermal ALD method isemployed. With the plasma ALD method, for example, the film can beformed without decreasing the deposition rate even at 100° C. or lower.Moreover, in the plasma ALD method, nitrogen radicals can be formed byplasma; thus, a nitride film as well as an oxide film can be formed.

In addition, oxidizability of an oxidizer can be enhanced by the plasmaALD method. Thus, precursors remaining in a plasma ALD film or organiccomponents released from precursors can be reduced. In addition, carbon,chlorine, hydrogen, and the like in the film can be reduced. Therefore,a film with low impurity concentration can be formed.

In the case of using the plasma ALD method, when radical species aregenerated, plasma can be generated from a place apart from the substratelike inductively coupled plasma (ICP) or the like, so that plasma damageto the substrate or a film on which the protective film is formed can beinhibited.

As described above, with the plasma ALD method, the film can bedeposited in the state where the process temperature can be lowered andthe coverage of the surface can be increased as compared with otherdeposition methods. Thus, entry of water and hydrogen from the outsidecan be inhibited, leading to an improvement of the reliability ofcharacteristics of the transistor.

<ALD apparatus>

FIG. 5A illustrates an example of a deposition apparatus utilizing anALD method. The deposition apparatus utilizing an ALD method includes adeposition chamber (chamber 1701), source material supply portions 1711a and 1711 b, high-speed valves 1712 a and 1712 b which are flow ratecontrollers, source material introduction ports 1713 a and 1713 b, asource material exhaust port 1714, and an evacuation unit 1715. Thesource material introduction ports 1713 a and 1713 b provided in thechamber 1701 are connected to the source material supply portions 1711 aand 1711 b, respectively, through supply tubes and valves. The sourcematerial exhaust port 1714 is connected to the evacuation unit 1715through an exhaust tube, a valve, and a pressure controller.

A substrate holder 1716 with a heater is provided in the chamber, and asubstrate 1700 over which a film is formed is provided over thesubstrate holder.

In the source material supply portions 1711 a and 1711 b, a source gasis formed from a solid source material or a liquid source material byusing a vaporizer, a heating unit, or the like. Alternatively, thesource material supply portions 1711 a and 1711 b may supply a sourcegas.

Although two source material supply portions 1711 a and 1711 b areprovided as an example, without limitation thereon, three or more sourcematerial supply portions may be provided. The high-speed valves 1712 aand 1712 b can be accurately controlled by time, and a source gas and aninert gas are supplied by the high-speed valves 1712 a and 1712 b. Thehigh-speed valves 1712 a and 1712 b are flow rate controllers for asource gas, and can also be referred to as flow rate controllers for aninert gas.

In the deposition apparatus illustrated in FIG. 5A, a thin film isformed over a surface of the substrate 1700 in the following manner: thesubstrate 1700 is transferred to put on the substrate holder 1716, thechamber 1701 is sealed, the substrate 1700 is heated to a desiredtemperature (e.g., higher than or equal to 100° C. or higher than orequal to 150° C.) by heating the substrate holder 1716 with a heater;and supply of a source gas, evacuation with the evacuation unit 1715,supply of an inert gas, and evacuation with the evacuation unit 1715 arerepeated.

In the deposition apparatus illustrated in FIG. 5A, an insulating layerformed using an oxide (including a composite oxide) containing one ormore elements selected from hafnium, aluminum, tantalum, zirconium, andthe like can be formed by selecting a source material (e.g., a volatileorganometallic compound) used for the source material supply portions1711 a and 1711 b appropriately. Specifically, it is possible to use aninsulating layer formed using hafnium oxide, an insulating layer formedusing aluminum oxide, an insulating layer formed using hafnium silicate,or an insulating layer formed using aluminum silicate. Alternatively, athin film, e.g., a metal layer such as a tungsten layer or a titaniumlayer, or a nitride layer such as a titanium nitride layer can be formedby selecting a source material (e.g., a volatile organometalliccompound) used for the source material supply portions 1711 a and 1711 bappropriately.

For example, in the case where a hafnium oxide layer is formed by adeposition apparatus using an ALD method, two kinds of gases, i.e.,ozone (O₃) as an oxidizer and a source gas which is obtained byvaporizing liquid containing a solvent and a hafnium precursor compound(hafnium alkoxide or hafnium amide such astetrakis(dimethylamide)hafnium (TDMAH)) are used. In this case, thefirst source gas supplied from the source material supply portion 1711 ais TDMAH, and the second source gas supplied from the source materialsupply portion 1711 b is ozone. Note that the chemical formula oftetrakis(dimethylamide)hafnium is Hf[N(CH₃)₂]₄. Examples of anothermaterial include tetrakis(ethylmethylamide)hafnium. Note that nitrogenhas a function of eliminating charge trap states. Therefore, when thesource gas contains nitrogen, a hafnium oxide film having low density ofcharge trap states can be formed.

In the case where an aluminum oxide layer is formed by a depositionapparatus utilizing an ALD method, two kinds of gases, e.g., H₂O as anoxidizer and a source gas which is obtained by vaporizing liquidcontaining a solvent and an aluminum precursor compound (e.g.,trimethylaluminum (TMA)) are used. In this case, the first source gassupplied from the source material supply portion 1711 a is TMA, and thesecond source gas supplied from the source material supply portion 1711b is H₂O. Note that the chemical formula of trimethylaluminum isAl(CH₃)₃. Examples of another material liquid includetris(dimethylamide)aluminum, triisobutylaluminum, and aluminumtris(2,2,6,6-tetramethyl-3,5-heptanedionate).

For example, in the case where a silicon oxide film is formed by adeposition apparatus using an ALD method, hexachlorodisilane is adsorbedon a surface where a film is to be formed, chlorine contained in theadsorbate is removed, and radicals of an oxidizing gas (e.g., O₂ ordinitrogen monoxide) are supplied to react with the adsorbate.

For example, in the case where a tungsten film is formed using adeposition apparatus employing ALD, a WF₆ gas and a B₂H₆ gas aresequentially introduced plural times to form an initial tungsten film,and then a WF₆ gas and an H₂ gas are introduced at a time, so that atungsten film is formed. Note that an SiH₄ gas may be used instead of aB₂H₆ gas.

For example, in the case where an oxide semiconductor film, e.g., anIn—Ga—Zn—O film is formed using a deposition apparatus employing ALD, anIn(CH₃)₃ gas and an O₃ gas are sequentially introduced plural times toform an In—O layer, a Ga(CH₃)₃ gas and an O₃ gas are introduced at atime to form a GaO layer, and then a Zn(CH₃)₂ gas and an O₃ gas areintroduced at a time to form a ZnO layer. Note that the order of theselayers is not limited to this example. A mixed compound layer such as anIn—Ga—O layer, an In—Zn—O layer, or a Ga—Zn—O layer may be formed bymixing these gases. Note that although an H₂O gas which is obtained bybubbling water with an inert gas such as Ar may be used instead of an O₃gas, it is preferable to use an O₃ gas, which does not contain H.Instead of an In(CH₃)₃ gas, an In(C₂H₅)₃ gas may be used. Instead of aGa(CH₃)₃ gas, a Ga(C₂H₅)₃ gas may be used. A Zn(CH₃)₂ gas may be used.

<<Multi-Chamber Manufacturing Apparatus>>

FIG. 5B illustrates an example of a multi-chamber manufacturingapparatus including at least one deposition apparatus illustrated inFIG. 5A.

In the manufacturing apparatus illustrated in FIG. 5B, a stack of filmscan be successively formed without exposure to the air, and entry ofimpurities is prevented and throughput is improved.

The manufacturing apparatus illustrated in FIG. 5B includes at least aload chamber 1702, a transfer chamber 1720, a pretreatment chamber 1703,a chamber 1701 which is a deposition chamber, and an unload chamber1706. Note that in order to prevent attachment of moisture, the chambersof the manufacturing apparatus (including the load chamber, thetreatment chamber, the transfer chamber, the deposition chamber, theunload chamber, and the like) are preferably filled with an inert gas(such as a nitrogen gas) whose dew point is controlled, more preferablymaintain reduced pressure.

The chambers 1704 and 1705 may be deposition apparatuses utilizing anALD method like the chamber 1701, deposition apparatuses utilizing aplasma CVD method, deposition apparatuses utilizing a sputtering method,or deposition apparatuses utilizing a metal organic chemical vapordeposition (MOCVD) method.

For example, an example in which a stack of films is formed under acondition that the chamber 1704 is a deposition apparatus utilizing aplasma CVD method and the chamber 1705 is a deposition apparatusutilizing an MOCVD method is shown below.

Although FIG. 5B shows an example in which a top view of the transferchamber 1720 is a hexagon, a manufacturing apparatus in which the topsurface shape is set to a polygon having more than six corners and morechambers are connected depending on the number of layers of a stack maybe used. The top surface shape of the substrate is rectangular in FIG.5B; however, there is no particular limitation on the top surface shapeof the substrate. Although FIG. 5B shows an example of the single wafertype, a batch-type deposition apparatus in which films are deposited ona plurality of substrates at a time may be used.

<Formation of Insulating Layer 110>

First, the insulating layer 110 is formed over the substrate 100. Theinsulating layer 110 can be formed by a plasma CVD method, a thermal CVDmethod (an MOCVD method, an ALD method), a sputtering method, or thelike with use of an oxide insulating film of aluminum oxide, magnesiumoxide, silicon oxide, silicon oxynitride, gallium oxide, germaniumoxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide,hafnium oxide, tantalum oxide, or the like; a nitride insulating film ofsilicon nitride, silicon nitride oxide, aluminum nitride, aluminumnitride oxide, or the like; or a mixed material of any of these.Alternatively, these materials may be stacked, in which case at least anupper layer of the stacked layer which is in contact with a first oxideinsulating film to be the oxide insulating layer 121 later is preferablyformed using a material containing excess oxygen that can serve as asupply source of oxygen to the oxide semiconductor layer 122.

As the insulating layer 110, for example, a 100-nm-thick siliconoxynitride film can be formed by a plasma CVD method.

Next, first heat treatment may be performed to release water, hydrogen,or the like contained in the insulating layer 110. As a result, theconcentration of water, hydrogen, or the like contained in theinsulating layer 110 can be reduced. The heat treatment can reduce theamount of water, hydrogen, or the like diffused into the first oxideinsulating film that is to be formed later.

<Formation of First Oxide Insulating Film and Oxide Semiconductor Film>

Then, the first oxide insulating film to be the oxide insulating layer121 later and an oxide semiconductor film to be the oxide semiconductorlayer 122 later are formed over the insulating layer 110. The firstoxide insulating film and the oxide semiconductor film can be formed bya sputtering method, an MOCVD method, a PLD method, or the like, andespecially, a sputtering method is preferable. As a sputtering method,an RF sputtering method, a DC sputtering method, an AC sputteringmethod, or the like can be used. In addition, a facing-target-typesputtering method (also referred to as a counter-electrode-typesputtering method, a gas phase sputtering method, and a vapor depositionsputtering (VDSP) method) is used, whereby plasma damage at thedeposition can be reduced.

When the first oxide insulating film is formed by a sputtering method,it is preferable that each chamber of the sputtering apparatus be ableto be evacuated to a high vacuum (about 5×10⁻⁷ Pa to 1×10⁻Pa) by anadsorption vacuum pump such as a cryopump and that the chamber be ableto heat a substrate over which a film is to be deposited to 100° C. orhigher, preferably 400° C. or higher so that water and the like actingas impurities in the oxide semiconductor can be removed as much aspossible. Alternatively, a combination of a turbo molecular pump and acold trap is preferably used to prevent back-flow of a gas containing acarbon component, moisture, or the like from an exhaust system into thechamber. Alternatively, a combination of a turbo molecular pump and acryopump may be used as an exhaust system.

Not only high vacuum evacuation in a chamber but also high purity of asputtering gas is necessary to obtain a high-purity intrinsic oxidesemiconductor. When a highly purified gas having a dew point of −40° C.or lower, preferably −80° C. or lower, more preferably −100° C. or loweris used as an oxygen gas or an argon gas used as a sputtering gas,moisture or the like can be prevented from entering an oxidesemiconductor as much as possible.

As a sputtering gas, a rare gas (typically argon), oxygen, or a mixedgas of a rare gas and oxygen is used as appropriate. In the case ofusing the mixed gas of a rare gas and oxygen, the proportion of oxygento a rare gas is preferably increased.

Note that, for example, in the case where the oxide semiconductor filmis formed by a sputtering method at a substrate temperature higher thanor equal to 150° C. and lower than or equal to 750° C., preferablyhigher than or equal to 150° C. and lower than or equal to 450° C.,further preferably higher than or equal to 200° C. and lower than orequal to 420° C., the oxide semiconductor film can be a CAAC-OS film.

The material of the first oxide insulating film is selected so that thefirst oxide insulating film can have a lower electron affinity than theoxide semiconductor film.

The indium content of the oxide semiconductor film is preferably higherthan those of the first oxide insulating film and a second oxideinsulating film. In an oxide semiconductor, the s orbital of heavy metalmainly contributes to carrier transfer, and when the proportion of In inthe oxide semiconductor is increased, overlap of the s orbitals islikely to be increased. Therefore, an oxide having a composition inwhich the proportion of In is higher than that of Ga has higher mobilitythan an oxide having a composition in which the proportion of In isequal to or lower than that of Ga. Thus, with the use of an oxide havinga high indium content for the oxide semiconductor layer 122, atransistor having high mobility can be achieved.

When a sputtering method is used to form the first oxide insulating filmand the oxide semiconductor film, the first oxide insulating film andthe oxide semiconductor film can be successively formed without exposingto the air with use of a multi-chamber sputtering apparatus. In thatcase, entry of unnecessary impurities and the like into the interfacebetween the first oxide insulating film and the oxide semiconductor filmcan be prevented and the density of interface states can be reducedaccordingly. Thus, the electrical characteristics of a transistor can bestabilized, particularly in a reliability test.

If the oxide semiconductor film is damaged, the oxide semiconductorlayer 122, which is a main conduction path, can keep a distance from thedamaged part thanks to the existence of the oxide insulating layer 121.Thus, the electrical characteristics of a transistor can be stabilized,particularly in a reliability test.

As the first oxide insulating film, a 20-nm-thick oxide insulating filmwhich is formed by a sputtering method using a target having an atomicratio of In:Ga:Zn=1:3:4 can be used. In addition, as the oxidesemiconductor film, a 15-nm-thick oxide semiconductor film which isformed by a sputtering method using a target having an atomic ratio ofIn:Ga:Zn=1:1:1 can be used.

The amount of oxygen vacancies in the oxide semiconductor film can bereduced by performing second heat treatment after the first oxideinsulating film and the oxide semiconductor film are formed.

The temperature of the second heat treatment is higher than or equal to250° C. and lower than the strain point of the substrate, preferablyhigher than or equal to 300° C. and lower than or equal to 650° C.,further preferably higher than or equal to 350° C. and lower than orequal to 550° C.

The second heat treatment is performed under an inert gas atmospherecontaining nitrogen or a rare gas such as helium, neon, argon, xenon, orkrypton. Further, after heat treatment performed in an inert gasatmosphere, heat treatment may be additionally performed in an oxygenatmosphere or a dry air atmosphere (air whose dew point is lower than orequal to −80° C., preferably lower than or equal to −100° C., furtherpreferably lower than or equal to −120° C.). The treatment may beperformed under reduced pressure. Note that it is preferable thathydrogen, water, and the like be not contained in an inert gas andoxygen, like the dry air, and the dew point is preferably lower than orequal to −80° C., further preferably lower than or equal to −100° C. Thetreatment time is 3 minutes to 24 hours.

In the heat treatment, instead of an electric furnace, any device forheating an object by heat conduction or heat radiation from a heatingelement, such as a resistance heating element, may be used. For example,an RTA (rapid thermal annealing) apparatus, such as a GRTA (gas rapidthermal annealing) apparatus or an LRTA (lamp rapid thermal annealing)apparatus, can be used. The LRTA apparatus is an apparatus for heatingan object to be processed by radiation of light (an electromagneticwave) emitted from a lamp, such as a halogen lamp, a metal halide lamp,a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or ahigh pressure mercury lamp. The GRTA apparatus is an apparatus for heattreatment using a high-temperature gas. As the high-temperature gas, aninert gas, such as nitrogen or a rare gas like argon, is used.

Note that the second heat treatment may be performed after etching forforming the oxide insulating layer 121 and the oxide semiconductor layer122 described later.

For example, after heat treatment is performed at 450° C. for one hourin a nitrogen atmosphere, heat treatment is performed at 450° C. for onehour in an oxygen atmosphere.

Through the above-described steps, oxygen vacancies and impurities suchas hydrogen and water in the oxide semiconductor films can be reduced.The oxide semiconductor films can have low density of localized states.

<Formation of First Conductive Film>

Next, a first conductive film to be the source electrode layer 130 andthe drain electrode layer 140 is formed over the oxide semiconductorlayer 122. The first conductive film is formed by a sputtering method, achemical vapor deposition (CVD) method such as a metal organic chemicalvapor deposition (MOCVD) method, a metal chemical deposition method, anatomic layer deposition (ALD) method, or a plasma-enhanced chemicalvapor deposition (PECVD) method, an evaporation method, a pulsed laserdeposition (PLD) method, or the like.

As a preferable material of the first conductive film, a single-layerstructure or a layered structure of a conductive film containing alow-resistance material selected from copper (Cu), tungsten (W),molybdenum (Mo), gold (Au), aluminum (Al), manganese (Mn), titanium(Ti), tantalum (Ta), nickel (Ni), chromium (Cr), lead (Pb), tin (Sn),iron (Fe), cobalt (Co), ruthenium (Ru), platinum (Pt), iridium (Ir), andstrontium (Sr), an alloy of such a low-resistance material, or acompound containing such a material as its main component. For example,in the case of stacking layers, the lower conductive layer which is incontact with the oxide semiconductor layer 122 contains a material whichis easily combined with oxygen, and the upper conductive layer containsa highly oxidation-resistant material. It is preferable to use ahigh-melting-point material which has both heat resistance andconductivity, such as tungsten or molybdenum. In addition, alow-resistance conductive material, such as aluminum or copper, ispreferable. A Cu—Mn alloy is also preferable, in which case manganeseoxide formed at the interface with an insulator containing oxygen has afunction of preventing Cu diffusion.

As the first conductive film, for example, a tungsten film having athickness of 20 nm to 100 nm can be formed by a sputtering method.

A conductive layer 130 b formed by processing the first conductive filmcan have a function of a hard mask in the subsequent step and a functionof a source electrode and a drain electrode; thus, the number of stepscan be reduced. Thus, the semiconductor manufacturing process can beshortened.

<Formation of Oxide Insulating Layer 121 and Oxide Semiconductor Layer122>

Then, a resist mask is formed through a lithography process. The firstconductive film is selectively etched using the resist mask, so that theconductive layer 130 b is formed. The resist over the conductive layer130 b is removed. The oxide semiconductor film and the first oxideinsulating film are selectively etched using the conductive layer 130 bas a hard mask, so that the island-shaped oxide semiconductor layer 122and oxide insulating layer 121 can be formed (see FIGS. 6A and 6B). Dryetching can be used here. Note that the use of the conductive layer 130b as a hard mask for etching for the oxide semiconductor layer canreduce edge roughness of the etched oxide semiconductor layer ascompared with the case of using a resist mask.

<Formation of Second Insulating Film>

Next, a second insulating film to be the insulating layer 175 later isformed over the insulating layer 110 and the conductive layer 130 b. Thesecond insulating film can be formed in a manner similar to that of theinsulating layer 110.

The second insulating film can be formed by a plasma CVD method, athermal CVD method (an MOCVD method, an ALD method), a sputteringmethod, or the like with use of an oxide insulating film of aluminumoxide, magnesium oxide, silicon oxide, silicon oxynitride, galliumoxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide,neodymium oxide, hafnium oxide, tantalum oxide, or the like; a nitrideinsulating film of silicon nitride, silicon nitride oxide, aluminumnitride, aluminum nitride oxide, or the like; or a mixed material of anyof these. Alternatively, a stack of any of the above materials may beused.

<Planarization of Second Insulating Film>

Then, planarization treatment is performed on the second insulatingfilm, so that an insulating layer 175 b is formed. The planarizationtreatment can be performed by a chemical mechanical polishing (CMP)method, a dry etching method, a reflow method, or the like. In the casewhere the CMP method is used, a film whose composition is different fromthat of the second insulating film is formed over the second insulatingfilm, whereby the thickness of the insulating layer 175 b in thesubstrate surface after the CMP treatment can be uniform.

<Formation of Groove Portion, Source Electrode Layer 130, and DrainElectrode Layer 140>

Next, a resist mask 176 is formed over the insulating layer 175 b by alithography process (see FIGS. 7A and 7B). Note that the lithographyprocess may be performed after an organic film is applied to theinsulating layer 175 b or an organic film is applied to the resist. Theorganic film can contain propylene glycolmonomethyl ether, ethyllactate, or the like. The use of the organic film leads to, in additionto an anti-reflection effect during light exposure, an improvement inadhesion between a resist and a film, an improvement in resolution, andthe like. The organic film can be used in another process.

Note that in the case where a transistor having an extremely shortchannel length is formed, at least the conductive layer 130 b in aregion to divide the conductive layer 130 b to be the source electrodelayer 130 and the drain electrode layer 140 is etched using a resistmask that is processed by a method suitable for micropatterning, such aselectron beam exposure, liquid immersion exposure, or extremeultraviolet (EUV) exposure. Note that in the case of forming the resistmask by electron beam exposure, a positive resist mask is used, so thatan exposed region can be minimized and throughput can be improved. Inthe above manner, a transistor having a channel length of 100 nm orless, further, 30 nm or less can be formed. Alternatively, minuteprocessing may be performed by an exposure technology which uses X-raysor the like.

With the resist mask, groove processing is performed on the insulatinglayer 175 b by a dry etching method. Through the groove processing, theresist mask gradually recedes to become a resist mask 177 (see FIGS. 8Aand 8B). Furthermore, the shape of the resist is changed by heatgenerated due to the dry etching process to have a protrusion like eaves(the resist mask 178). In this state, the etching process furtherproceeds, whereby the groove portion 174 is formed in the insulatinglayer 175 b.

Then, the exposed conductive layer 130 b is selectively etched to bedivided, so that the source electrode layer 130 and the drain electrodelayer 140 can be formed (see FIGS. 9A and 9B).

Note that the processing method of the groove portion 174 is not limitedto the above method. For example, not only the resist mask but also ahard mask may be used, or a half-tone mask may be used in a lithographyprocess to control the shape of the resist mask. Alternatively, theshape of the mask may be controlled by nanoimprint lithography. Thenanoimprint lithography can be used in another process.

After the source electrode layer 130 and the drain electrode layer 140are formed, cleaning treatment may be performed to remove an etchingresidue. The cleaning treatment can prevent a short circuit between thesource electrode layer 130 and the drain electrode layer 140. Thecleaning treatment can be performed using an alkaline solution such as atetramethylammonium hydroxide (TMAH) solution, an acidic solution suchas hydrofluoric acid, an oxalic acid solution, or a phosphoric acidsolution. By the cleaning treatment, part of the oxide semiconductorlayer 122 is etched to have a depression.

For example, the silicon oxynitride film formed as the second insulatingfilm is planarized, a resist mask is formed over the silicon oxynitridefilm by a lithography method, and an opening is formed in the siliconoxynitride film with the resist mask by a dry etching method using a gascontaining carbon, fluorine, or the like. Then, dry etching using a gascontaining chlorine, fluorine, or the like is performed, whereby thesource electrode layer 130 and the drain electrode layer 140 can beformed.

<Formation of Second Oxide Insulating Film 123 a>

Next, a second oxide insulating film 123 a to be the oxide insulatinglayer 123 is formed over the oxide semiconductor layer 122 and theinsulating layer 175. The second oxide insulating film 123 a can beformed in a manner similar to that of the first oxide insulating film.The materials can be selected such that the electron affinity of thesecond oxide insulating film 123 a is smaller than that of the oxidesemiconductor film.

Furthermore, if the second oxide insulating film 123 a is formed by along throw sputtering method, the embeddability of the second oxideinsulating film 123 a in the groove portion 174 can be improved.

For example, as the second oxide insulating film 123 a, a 5-nm-thickoxide insulating film which is formed by a sputtering method using atarget having an atomic ratio of In:Ga:Zn=1:3:2 can be used.

<Formation of Third Insulating Film 150 a>

Next, a third insulating film 150 a to be the gate insulating layer 150is formed over the second oxide insulating film 123 a. The thirdinsulating film 150 a can be formed using aluminum oxide, magnesiumoxide, silicon oxide, silicon oxynitride, silicon nitride oxide, siliconnitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide,lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, or thelike. The third insulating film 150 a may be a stack containing any ofthese materials. The third insulating film 150 a can be formed by asputtering method, a CVD method (e.g., a plasma CVD method, an MOCVDmethod, or an ALD method), an MBE method, or the like. The thirdinsulating film 150 a can be formed by a method similar to that of theinsulating layer 110 as appropriate.

For example, as the third insulating film 150 a, a 10-nm-thick siliconoxynitride film can be formed by a plasma CVD method.

<Formation of Second Conductive Film 160 a>

Next, a second conductive film 160 a to be the gate electrode layer 160is formed over the third insulating film 150 a (see FIGS. 10A and 10B).For example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co),nickel (Ni), copper (Cu), yttrium (Y), zirconium (Zr), molybdenum (Mo),ruthenium (Ru), silver (Ag), tantalum (Ta), and tungsten (W), or analloy material containing any of these as its main component can be usedfor the second conductive film 160 a. The second conductive film 160 acan be formed by a sputtering method, a CVD method (e.g., a plasma CVDmethod, an MOCVD method, or an ALD method), an MBE method, anevaporation method, a plating method, or the like. The second conductivefilm 160 a may be formed using a conductive film containing nitrogen ora stack including the above conductive film and a conductive filmcontaining nitrogen.

For example, a stack of a 10-nm-thick titanium nitride film formed by anALD method and a 150-nm-thick tungsten film formed by a metal CVD methodcan be used.

<Planarization Treatment>

Then, planarization treatment is performed. The planarization treatmentcan be performed by a CMP method, a dry etching method, or the like. Theplanarization treatment may be terminated at the time when the thirdinsulating film 150 a is exposed, may be terminated at the time when thesecond oxide insulating film 123 a is exposed, or may be terminated atthe time when the insulating layer 175 is exposed. Accordingly, the gateelectrode layer 160, the gate insulating layer 150, and the oxideinsulating layer 123 can be formed (see FIGS. 11A and 11B).

In the case where the second oxide insulating film 123 a or the thirdinsulating film 150 a is provided over the insulating layer 175 that hasbeen planarized, another resist mask may be used for the processing. Theresist mask is formed over the second oxide insulating film 123 a or thethird insulating film 150 a by a lithography process. The mask has alarger area than that of the top surface portion of the gate electrodelayer 160. The third insulating film 150 a and the second oxideinsulating film 123 a are selectively etched using the mask, so that thegate insulating layer 150 and the oxide insulating layer 123 can beformed.

In the transistor 10, by providing the oxide insulating layer 123 inwhich oxygen vacancies are unlikely to occur, release of oxygen fromside surfaces of the oxide semiconductor layer 122 in the channel widthdirection is suppressed, so that generation of oxygen vacancies can besuppressed. As a result, a transistor which has improved electricalcharacteristics and high reliability can be provided.

<Formation of Insulating Layer 170>

Next, the insulating layer 170 is formed over the insulating layer 175,the oxide insulating layer 123, the gate insulating layer 150, and thegate electrode layer 160 (see FIGS. 12A and 12B). The insulating layer170 may have a single-layer structure or a stacked-layer structure. Theinsulating layer 170 can be formed using a material, a method, and thelike similar to those of the insulating layer 110.

The insulating layer 170 is preferably an aluminum oxide film formed bya sputtering method. A sputtering gas used for forming the aluminumoxide film preferably contains an oxygen gas. The oxygen gas iscontained at 1 vol. % or more and 100 vol. % or less, preferably 4 vol.% or more and 100 vol. % or less, further preferably 10 vol. % or moreand 100 vol. % or less. When oxygen is contained at 1 vol. % or more,the insulating layer 170 can contain excess oxygen or excess oxygen canbe supplied to insulating layers in contact with the insulating layer170.

For example, the insulating layer 170 having a thickness from 20 nm to40 nm can be formed using aluminum oxide as a sputtering target and asputtering gas that contains 50 vol. % of oxygen gas.

Next, heat treatment may be performed. The temperature of the heattreatment is typically higher than or equal to 150° C. and lower thanthe strain point of the substrate, preferably higher than or equal to250° C. and lower than or equal to 500° C., further preferably higherthan or equal to 300° C. and lower than or equal to 450° C. By the heattreatment, oxygen added to an insulating layer (e.g., the insulatinglayer 175) is diffused and moved to the oxide semiconductor layer 122,and oxygen vacancies in the oxide semiconductor layer 122 can be filledwith the oxygen.

In this embodiment, heat treatment is performed at 400° C. in an oxygenatmosphere for one hour.

Note that heat treatment may be performed in other processes. Throughheat treatment, defects in a film can be repaired, and the density ofinterface states can be reduced.

<Addition of Oxygen>

Oxygen may be added to the insulating layer 110 and the insulating layer175, the first oxide insulating film and the second oxide insulatingfilm 123 a, or another insulating layer. As the oxygen that is added, atleast one kind selected from oxygen radicals, oxygen atoms, oxygenatomic ions, oxygen molecular ions, and the like is used. As a methodfor adding the oxygen, an ion doping method, an ion implantation method,a plasma immersion ion implantation method, or the like can be used.

In the case of using an ion implantation method as the method for addingoxygen, oxygen atomic ions or oxygen molecular ions can be used. The useof oxygen molecular ions can reduce damage to a film to which oxygen isadded. Oxygen molecular ions are broken down into oxygen atomic ions atthe surface of the film to which oxygen is added, and the oxygen atomicions are added. Since energy for breaking oxygen molecules down intooxygen atoms is used, the energy per oxygen atomic ion in the case ofadding oxygen molecular ions to the film to which oxygen is added islower than that in the case of adding oxygen atomic ions to the film towhich oxygen is added. Therefore, damage to the film to which oxygen isadded can be reduced.

By using oxygen molecular ions, the energy of each oxygen atomic ioninjected to the film to which oxygen is added is lowered, which makesthe injected oxygen atomic ion be positioned in a shallow region.Accordingly, oxygen atoms easily move by later heat treatment, so thatmore oxygen can be supplied to an oxide semiconductor film.

In the case of injecting oxygen molecular ions, the energy per oxygenatomic ion is low as compared with the case of injecting oxygen atomicions. Thus, by using oxygen molecular ions for injection, theacceleration voltage can be increased and throughput can be increased.Moreover, by using oxygen molecular ions for injection, the dose can behalf of the amount that is necessary in the case of using oxygen atomicions. As a result, throughput can be increased.

In the case of adding oxygen to the film to which oxygen is added, it ispreferable that oxygen be added to the film to which oxygen is added sothat a peak of the concentration profile of oxygen atomic ions islocated in the film to which oxygen is added. In that case, theacceleration voltage for implantation can be lowered as compared to thecase where oxygen atomic ions are implanted, and damage to the film towhich oxygen is added can be reduced. In other words, defects in thefilm to which oxygen is added can be reduced, and variations inelectrical characteristics of the transistor can be suppressed.Furthermore, in the case where oxygen is added to the film to whichoxygen is added so that the amount of added oxygen atoms at theinterface between the insulating layer 110 and the oxide insulatinglayer 121 is less than 1×10²¹ atoms/cm³, less than 1×10²⁰ atoms/cm³, orless than 1×10¹⁹ atoms/cm³, the amount of oxygen added to the insulatinglayer 110 can be reduced. As a result, damage to the film to whichoxygen is added can be reduced, suppressing variation in the electricalcharacteristics of the transistor.

Plasma treatment (plasma immersion ion implantation method) in which thefilm to which oxygen is added is exposed to plasma generated in anatmosphere containing oxygen may be performed, to add oxygen to the filmto which oxygen is added. As the atmosphere containing oxygen, anatmosphere containing an oxidation gas such as oxygen, ozone, dinitrogenmonoxide, or nitrogen dioxide can be given. Note that it is preferablethat the film to which oxygen is added be exposed to plasma generated ina state where bias is applied on the substrate 100 side because theamount of oxygen added to the film to which oxygen is added can beincreased. As an example of an apparatus with which such plasmatreatment is performed, an ashing apparatus is given.

For example, oxygen molecular ions can be added to the first oxideinsulating film by an ion implantation method with a dose of 1×10¹⁶/cm²at an acceleration voltage of 5 kV.

Through the above-described steps, the density of localized states ofthe oxide semiconductor films is lowered, and thus a transistor withexcellent electrical characteristics can be manufactured. In addition, ahighly reliable transistor in which variations in electricalcharacteristics with time or variations in electrical characteristicsdue to a stress test are reduced can be manufactured.

Note that the shape of the transistor is not limited to theabove-described structure. Modification examples of the transistor 10and a structure example different from that of the transistor 10 aredescribed below.

<Modification Example 1 of Transistor 10: Transistor 11>

A transistor 11 with a shape different from that of the transistor 10illustrated in FIGS. 1A and 1B will be described with reference to FIGS.13A and 13B.

FIGS. 13A and 13B are a top view and a cross-sectional view of thetransistor 11. FIG. 13A is a top view of the transistor 11 and FIG. 13Bis a cross-sectional view taken along dashed-dotted line A1-A2 anddashed-dotted line A3-A4 in FIG. 13A.

As illustrated in FIG. 15B, which is an enlarged view, the transistor 11is different from the transistor 10 (see FIG. 15A) in that the sidesurface portion of the gate electrode layer 160 has a taper angle θ1 anddoes not have an inflection point. With such a structure, theembeddability of each layer can be improved.

<Modification Example 2 of Transistor 10: Transistor 12>

A transistor 12 with a different shape from that of the transistor 10illustrated in FIGS. 1A and 1B will be described with reference to FIGS.14A and 14B.

FIGS. 14A and 14B are a top view and a cross-sectional view of thetransistor 12. FIG. 14A is a top view of the transistor 12 and FIG. 14Bis a cross-sectional view taken along dashed-dotted line A1-A2 anddashed-dotted line A3-A4 in FIG. 14A.

As illustrated in FIG. 15C, which is an enlarged view, the transistor 12is different from the transistor 10 in that the side surface portion ofthe gate electrode layer 160 has the taper angle θ1 and an inflectionpoint P1 and a width L1 in an upper region of the gate electrode layer160 is larger than a width L2 in a lower region of the gate electrodelayer 160.

The manufacturing method of the transistor described in this embodimentcan be easily introduced into the conventional semiconductormanufacturing facilities.

This embodiment can be combined as appropriate with any of the otherembodiments and examples in this specification.

Embodiment 2

In this embodiment, a transistor 13 having a structure which isdifferent from the structures of the transistor 10, the transistor 11,and the transistor 12 described in Embodiment 1 and a method formanufacturing the transistor 13 will be described.

FIGS. 16A and 16B are a top view and a cross-sectional view of thetransistor 13 of one embodiment of the present invention. FIG. 16A is atop view and FIG. 16B is a cross-sectional view taken alongdashed-dotted line A1-A2 and dashed-dotted line A3-A4 in FIG. 16A. InFIG. 16A, some components are scaled up or down in size or omitted foreasy understanding. In addition, the direction of dashed-dotted lineA1-A2 and the direction of dashed-dotted line A3-A4 are sometimesreferred to as a channel length direction and a channel width direction,respectively.

The transistor 13 is different from the transistor 10 in that in thegroove portion 174, the end portions of the bottom surface of theinsulating layer 175 protrudes from the end portion of each of thesource electrode layer 131 and the drain electrode layer 141 asillustrated in FIGS. 16A and 16B.

FIGS. 17A and 17B are enlarged views of the transistor 13. Thetransistor 13 includes the oxide insulating layer 123, the gateinsulating layer 150, and the gate electrode layer 160 (e.g., the gateelectrode layer 161 and the gate electrode layer 162) in the grooveportion 174. The gate electrode layer 160 includes a first region 171, asecond region 172, and a third region 173 that have different widths inthe groove portion 174. The first region 171 is positioned over thesecond region 172 and the third region 173, and the second region 172 ispositioned over the third region 173. The width L1 in the first regioncan be larger than or the same as the width L2 in the second region. Inaddition, a width L3 in the third region can be larger or smaller thanor the same as the width L2 in the second region.

Furthermore, in the case where an angle formed by a plane which isparallel to a substrate and a side surface portion of the gate electrodelayer 160 is referred to as a taper angle, the transistor 13 has a taperangle θ1 in the first region, a taper angle θ2 in the second region, anda taper angle 03 in the third region. In addition, in the transistor 13,the gate electrode layer 160 has an inflection point P1, an inflectionpoint P2, and an inflection point P3. Note that the transistor 13 canhave a shape including the inflection point P1 and the inflection pointP2 as illustrated in FIG. 17B.

Moreover, in the transistor 13, the side surface portions in the firstregion 171 and the third region 173 of the gate electrode layer 160 canextend beyond the tangent T2 obtained in the second region 172.

Furthermore, the gate electrode layer 160 has a shape which is narrow inthe middle. Alternatively, the gate electrode layer 160 of thetransistor 13 may have a round shape or a linear shape.

In the transistor 13 with such a shape, parasitic capacitance generatedbetween the gate electrode layer 160 and the source electrode layer 131or between the gate electrode layer 160 and the drain electrode layer141 can be further reduced. Thus, the cut-off frequency characteristicsof the transistor 13 are improved. That is, the high-speed response ofthe transistor 13 can be achieved.

<Manufacturing Method of Transistor 13>

A manufacturing method of the transistor 13 will be described below.Note that for steps similar to those of the transistor 10 described inEmbodiment 1, the description of the transistor is referred to.

As illustrated in FIGS. 8A and 8B, steps up to the formation of theinsulating layer 175 b and the conductive layer 130 b are performed.

Next, as illustrated in FIGS. 18A and 18B, the conductive layer 130 b isetched in the direction substantially perpendicular to a substratesurface to form the source electrode layer 131 and the drain electrodelayer 141. At this time, the oxide semiconductor layer 122 may beslightly etched or may be hardly etched.

Then, the second oxide insulating film 123 a, the third insulating film150 a, a conductive film 161 a, and a conductive film 162 a aresequentially formed (see FIGS. 19A and 19B), planarization treatment isperformed (see FIGS. 20A and 20B), and the insulating layer 170 isformed, whereby the transistor 13 is formed (see FIGS. 21A and 21B).

This embodiment can be combined as appropriate with any of the otherembodiments and examples in this specification.

Embodiment 3 <Oxide Semiconductor Structure>

The structure of an oxide semiconductor is described in this embodiment.

An oxide semiconductor is classified into a single crystal oxidesemiconductor and a non-single-crystal oxide semiconductor. Examples ofa non-single-crystal oxide semiconductor include a c-axis alignedcrystalline oxide semiconductor (CAAC-OS), a polycrystalline oxidesemiconductor, a nanocrystalline oxide semiconductor (nc-OS), anamorphous-like oxide semiconductor (a-like OS), and an amorphous oxidesemiconductor.

From another perspective, an oxide semiconductor is classified into anamorphous oxide semiconductor and a crystalline oxide semiconductor.Examples of a crystalline oxide semiconductor include a single crystaloxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor,and an nc-OS.

It is known that an amorphous structure is generally defined as beingmetastable and unfixed, and being isotropic and having no non-uniformstructure. In other words, an amorphous structure has a flexible bondangle and a short-range order but does not have a long-range order.

This means that an inherently stable oxide semiconductor cannot beregarded as a completely amorphous oxide semiconductor. Moreover, anoxide semiconductor that is not isotropic (e.g., an oxide semiconductorthat has a periodic structure in a microscopic region) cannot beregarded as a completely amorphous oxide semiconductor. Note that ana-like OS has a periodic structure in a microscopic region, but at thesame time has a void and has an unstable structure. For this reason, ana-like OS has physical properties similar to those of an amorphous oxidesemiconductor.

<CAAC-OS>

First, a CAAC-OS is described.

A CAAC-OS is one of oxide semiconductors having a plurality of c-axisaligned crystal parts (also referred to as pellets).

In a combined analysis image (also referred to as a high-resolution TEMimage) of a bright-field image and a diffraction pattern of a CAAC-OS,which is obtained using a transmission electron microscope (TEM), aplurality of pellets can be observed. However, in the high-resolutionTEM image, a boundary between pellets, that is, a grain boundary is notclearly observed. Thus, in the CAAC-OS, a reduction in electron mobilitydue to the grain boundary is less likely to occur.

The CAAC-OS observed with a TEM is described below. FIG. 22A shows ahigh-resolution TEM image of a cross section of the CAAC-OS layer whichis observed from a direction substantially parallel to the samplesurface. The high-resolution TEM image is obtained with a sphericalaberration corrector function. The high-resolution TEM image obtainedwith a spherical aberration corrector function is particularly referredto as a Cs-corrected high-resolution TEM image. The Cs-correctedhigh-resolution TEM image can be obtained with, for example, an atomicresolution analytical electron microscope JEM-ARM200F manufactured byJEOL Ltd.

FIG. 22B is an enlarged Cs-corrected high-resolution TEM image of aregion (1) in FIG. 22A. FIG. 22B shows that metal atoms are arranged ina layered manner in a pellet. Each metal atom layer has a configurationreflecting unevenness of a surface over which the CAAC-OS is formed(hereinafter, the surface is referred to as a formation surface) or atop surface of the CAAC-OS, and is arranged parallel to the formationsurface or the top surface of the CAAC-OS.

As shown in FIG. 22B, the CAAC-OS film has a characteristic atomicarrangement. The characteristic atomic arrangement is denoted by anauxiliary line in FIG. 22C. FIGS. 22B and 22C prove that the size of apellet is greater than or equal to 1 nm or greater than or equal to 3nm, and the size of a space caused by tilt of the pellets isapproximately 0.8 nm. Therefore, the pellet can also be referred to as ananocrystal (nc). Furthermore, the CAAC-OS can also be referred to as anoxide semiconductor including c-axis aligned nanocrystals (CANC).

Here, according to the Cs-corrected high-resolution TEM images, theschematic arrangement of pellets 5100 of a CAAC-OS layer over asubstrate 5120 is illustrated by such a structure in which bricks orblocks are stacked (see FIG. 22D). The part in which the pellets aretilted as observed in FIG. 22C corresponds to a region 5161 shown inFIG. 22D.

FIG. 23A shows a Cs-corrected high-resolution TEM image of a plane ofthe CAAC-OS observed from a direction substantially perpendicular to thesample surface. FIGS. 23B, 23C, and 23D are enlarged Cs-correctedhigh-resolution TEM images of regions (1), (2), and (3) in FIG. 23A,respectively. FIGS. 23B, 23C, and 23D indicate that metal atoms arearranged in a triangular, quadrangular, or hexagonal configuration in apellet. However, there is no regularity of arrangement of metal atomsbetween different pellets.

Next, a CAAC-OS analyzed by X-ray diffraction (XRD) is described. Forexample, when the structure of a CAAC-OS including an InGaZnO₄ crystalis analyzed by an out-of-plane method, a peak appears at a diffractionangle (2θ) of around 31° as shown in FIG. 24A. This peak is derived fromthe (009) plane of the InGaZnO₄ crystal, which indicates that crystalsin the CAAC-OS have c-axis alignment, and that the c-axes are aligned ina direction substantially perpendicular to the formation surface or thetop surface of the CAAC-OS.

Note that in structural analysis of the CAAC-OS by an out-of-planemethod, another peak may appear when 2θ is around 36°, in addition tothe peak at 2θ of around 31°. The peak of 2θ at around 36° indicatesthat a crystal having no c-axis alignment is included in part of theCAAC-OS. It is preferable that in the CAAC-OS analyzed by anout-of-plane method, a peak appear when 2θ is around 31° and that a peaknot appear when 2θ is around 36°.

On the other hand, in structural analysis of the CAAC-OS by an in-planemethod in which an X-ray is incident on a sample in a directionsubstantially perpendicular to the c-axis, a peak appears when 2θ isaround 56°. This peak is derived from the (110) plane of the InGaZnO₄crystal. In the case of the CAAC-OS, when analysis (ϕscan) is performedwith 2θfixed at around 56° and with the sample rotated using a normalvector of the sample surface as an axis (ϕaxis), as shown in FIG. 24B, apeak is not clearly observed. In contrast, in the case of a singlecrystal oxide semiconductor of InGaZnO₄, whenfscan is performed with2θfixed at around 56°, as shown in FIG. 24C, six peaks which are derivedfrom crystal planes equivalent to the (110) plane are observed.Accordingly, the structural analysis using XRD shows that the directionsof a-axes and b-axes are irregularly oriented in the CAAC-OS.

Next, a CAAC-OS analyzed by electron diffraction is described. Forexample, when an electron beam with a probe diameter of 300 nm isincident on a CAAC-OS including an InGaZnO₄ crystal in a directionparallel to the sample surface, a diffraction pattern (also referred toas a selected-area transmission electron diffraction pattern) shown inFIG. 25A can be obtained. In this diffraction pattern, spots derivedfrom the (009) plane of an InGaZnO₄ crystal are included. Thus, theelectron diffraction also indicates that pellets included in the CAAC-OShave c-axis alignment and that the c-axes are aligned in a directionsubstantially perpendicular to the formation surface or the top surfaceof the CAAC-OS. Meanwhile, FIG. 25B shows a diffraction pattern obtainedin such a manner that an electron beam with a probe diameter of 300 nmis incident on the same sample in a direction perpendicular to thesample surface. As shown in FIG. 25B, a ring-like diffraction pattern isobserved. Thus, the electron diffraction also indicates that the a-axesand b-axes of the pellets included in the CAAC-OS do not have regularalignment. The first ring in FIG. 25B is considered to be derived fromthe (010) plane, the (100) plane, and the like of the InGaZnO₄ crystal.Furthermore, it is supposed that the second ring in FIG. 25B is derivedfrom the (110) plane and the like.

As described above, the CAAC-OS is an oxide semiconductor with highcrystallinity. Entry of impurities, formation of defects, or the likemight decrease the crystallinity of an oxide semiconductor. This meansthat the CAAC-OS has small amounts of impurities and defects (e.g.,oxygen vacancies).

Note that the impurity means an element other than the main componentsof the oxide semiconductor, such as hydrogen, carbon, silicon, or atransition metal element. For example, an element (specifically, siliconor the like) having higher strength of bonding to oxygen than a metalelement included in an oxide semiconductor extracts oxygen from theoxide semiconductor, which results in disorder of the atomic arrangementand reduced crystallinity of the oxide semiconductor. A heavy metal suchas iron or nickel, argon, carbon dioxide, or the like has a large atomicradius (or molecular radius), and thus disturbs the atomic arrangementof the oxide semiconductor and decreases crystallinity.

The characteristics of an oxide semiconductor having impurities ordefects might be changed by light, heat, or the like. Impuritiesincluded in the oxide semiconductor might serve as carrier traps orcarrier generation sources, for example. Furthermore, oxygen vacancy inthe oxide semiconductor serves as a carrier trap or serves as a carriergeneration source when hydrogen is captured therein.

The CAAC-OS having small amounts of impurities and oxygen vacancy is anoxide semiconductor with low carrier density (specifically, lower than8×10¹¹/cm³, preferably lower than 1×10¹¹/cm³, further preferably lowerthan 1×10¹⁰/cm³, and is higher than or equal to 1×10⁻⁹/cm³). Such anoxide semiconductor is referred to as a highly purified intrinsic orsubstantially highly purified intrinsic oxide semiconductor. A CAAC-OShas a low impurity concentration and a low density of defect states.Thus, the CAAC-OS can be referred to as an oxide semiconductor havingstable characteristics.

<nc-OS>

Next, an nc-OS is described.

An nc-OS has a region in which a crystal part is observed and a regionin which a crystal part is not clearly observed in a high-resolution TEMimage. In most cases, the size of a crystal part included in the nc-OSis greater than or equal to 1 nm and less than or equal to 10 nm, orgreater than or equal to 1 nm and less than or equal to 3 nm. Note thatan oxide semiconductor including a crystal part whose size is greaterthan 10 nm and less than or equal to 100 nm is sometimes referred to asa microcrystalline oxide semiconductor. In a high-resolution TEM imageof the nc-OS, for example, a grain boundary is not clearly observed insome cases. Note that there is a possibility that the origin of thenanocrystal is the same as that of a pellet in a CAAC-OS. Therefore, acrystal part of the nc-OS may be referred to as a pellet in thefollowing description.

In the nc-OS, a microscopic region (for example, a region with a sizegreater than or equal to 1 nm and less than or equal to 10 nm, inparticular, a region with a size greater than or equal to 1 nm and lessthan or equal to 3 nm) has a periodic atomic arrangement. There is noregularity of crystal orientation between different pellets in thenc-OS. Thus, the orientation of the whole film is not observed.Accordingly, the nc-OS cannot be distinguished from an a-like OS and anamorphous oxide semiconductor, depending on an analysis method. Forexample, when the nc-OS is analyzed by an out-of-plane method using anX-ray beam having a diameter larger than the size of a pellet, a peakwhich shows a crystal plane does not appear. Furthermore, a diffractionpattern like a halo pattern is observed when the nc-OS is subjected toelectron diffraction using an electron beam with a probe diameter (e.g.,50 nm or larger) that is larger than the size of a pellet. Meanwhile,spots appear in a nanobeam electron diffraction pattern of the nc-OSwhen an electron beam having a probe diameter close to or smaller thanthe size of a pellet is applied. Moreover, in a nanobeam electrondiffraction pattern of the nc-OS, regions with high luminance in acircular (ring) pattern are shown in some cases. Also in a nanobeamelectron diffraction pattern of the nc-OS layer, a plurality of spots isshown in a ring-like region in some cases.

Since there is no regularity of crystal orientation between the pellets(nanocrystals) as mentioned above, the nc-OS can also be referred to asan oxide semiconductor including random aligned nanocrystals (RANC) oran oxide semiconductor including non-aligned nanocrystals (NANC).

The nc-OS is an oxide semiconductor that has high regularity as comparedto an amorphous oxide semiconductor. Therefore, the nc-OS is likely tohave a lower density of defect states than an a-like OS and an amorphousoxide semiconductor. Note that there is no regularity of crystalorientation between different pellets in the nc-OS. Therefore, the nc-OShas a higher density of defect states than the CAAC-OS.

<a-like OS>

An a-like OS is an oxide semiconductor having a structure between thenc-OS and the amorphous oxide semiconductor.

In a high-resolution TEM image of the a-like OS, a void may be observed.Furthermore, in the high-resolution TEM image, there are a region wherea crystal part is clearly observed and a region where a crystal part isnot observed.

The a-like OS has an unstable structure because it includes a void. Toverify that an a-like OS has an unstable structure as compared with aCAAC-OS and an nc-OS, a change in structure caused by electronirradiation is described below.

An a-like OS (sample A), an nc-OS (sample B), and a CAAC-OS (sample C)are prepared as samples subjected to electron irradiation. Each of thesamples is an In—Ga—Zn oxide.

First, a high-resolution cross-sectional TEM image of each sample isobtained. The high-resolution cross-sectional TEM images show that allthe samples have crystal parts.

Note that which part is regarded as a crystal part is determined asfollows. It is known that a unit cell of the InGaZnO₄ crystal has astructure in which nine layers including three In—O layers and sixGa—Zn—O layers are stacked in the c-axis direction. The distance betweenthe adjacent layers is equivalent to the lattice spacing on the (009)plane (also referred to as d value). The value is calculated to be 0.29nm from crystal structural analysis. Accordingly, a portion where thelattice spacing between lattice fringes is greater than or equal to 0.28nm and less than or equal to 0.30 nm is regarded as a crystal part ofInGaZnO₄. Each of lattice fringes corresponds to the a-b plane of theInGaZnO₄ crystal.

FIG. 26 shows change in the average size of crystal parts (at 22 pointsto 45 points) in each sample. Note that the crystal part sizecorresponds to the length of a lattice fringe. FIG. 26 indicates thatthe crystal part size in the a-like OS increases with an increase in thecumulative electron dose. Specifically, as shown by (1) in FIG. 26, acrystal part of approximately 1.2 nm at the start of TEM observation(the crystal part is also referred to as an initial nucleus) grows to asize of approximately 2.6 nm at a cumulative electron dose of 4.2×10⁸e⁻/nm². In contrast, the crystal part size in the nc-OS and the CAAC-OSshows little change from the start of electron irradiation to acumulative electron dose of 4.2×10⁸ e⁻/nm². Specifically, as shown by(2) and (3) in FIG. 26, the average crystal sizes in an nc-OS and aCAAC-OS are approximately 1.4 nm and approximately 2.1 nm, respectively,regardless of the cumulative electron dose.

In this manner, growth of the crystal part in the a-like OS is inducedby electron irradiation. In contrast, in the nc-OS and the CAAC-OS,growth of the crystal part is hardly induced by electron irradiation.Therefore, the a-like OS has an unstable structure as compared with thenc-OS and the CAAC-OS.

The a-like OS has a lower density than the nc-OS and the CAAC-OS becauseit includes a void. Specifically, the density of the a-like OS is higherthan or equal to 78.6% and lower than 92.3% of the density of the singlecrystal oxide semiconductor having the same composition. The density ofeach of the nc-OS and the CAAC-OS is higher than or equal to 92.3% andlower than 100% of the density of the single crystal oxide semiconductorhaving the same composition. Note that it is difficult to deposit anoxide semiconductor having a density of lower than 78% of the density ofthe single crystal oxide semiconductor.

For example, in the case of an oxide semiconductor having an atomicratio of In:Ga:Zn=1:1:1, the density of single crystal InGaZnO₄ with arhombohedral crystal structure is 6.357 g/cm³. Accordingly, in the caseof the oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, thedensity of the a-like OS is higher than or equal to 5.0 g/cm³ and lowerthan 5.9 g/cm³. For example, in the case of the oxide semiconductorhaving an atomic ratio of In:Ga:Zn=1:1:1, the density of each of thenc-OS and the CAAC-OS is higher than or equal to 5.9 g/cm³ and lowerthan 6.3 g/cm³.

Note that there is a possibility that an oxide semiconductor having acertain composition cannot exist in a single crystal structure. In thatcase, single crystal oxide semiconductors with different compositionsare combined at an adequate ratio, which makes it possible to calculatedensity equivalent to that of a single crystal oxide semiconductor withthe desired composition. The density of a single crystal oxidesemiconductor having the desired composition can be calculated using aweighted average according to the combination ratio of the singlecrystal oxide semiconductors with different compositions. Note that itis preferable to use as few kinds of single crystal oxide semiconductorsas possible to calculate the density.

As described above, oxide semiconductors have various structures andvarious properties. Note that an oxide semiconductor may be a stackedlayer including two or more of an amorphous oxide semiconductor, ana-like OS, an nc-OS, and a CAAC-OS, for example.

Embodiment 4

In this embodiment, an example of a circuit including the transistor ofone embodiment of the present invention is described with reference todrawings.

<Cross-Sectional Structure>

FIG. 27A is a cross-sectional view of a semiconductor device of oneembodiment of the present invention. In FIG. 27A, X1-X2 direction andY1-Y2 direction represent a channel length direction and a channel widthdirection, respectively. The semiconductor device illustrated in FIG.27A includes a transistor 2200 containing a first semiconductor materialin a lower portion and a transistor 2100 containing a secondsemiconductor material in an upper portion. In FIG. 27A, an example isdescribed in which the transistor described in the above embodiment asan example is used as the transistor 2100 containing the secondsemiconductor material. A cross-sectional view of the transistors in achannel length direction is on the left side of a dashed-dotted line,and a cross-sectional view of the transistors in a channel widthdirection is on the right side of the dashed-dotted line.

Here, the first semiconductor material and the second semiconductormaterial are preferably materials having different band gaps. Forexample, the first semiconductor material can be a semiconductormaterial other than an oxide semiconductor (examples of such asemiconductor material include silicon (including strained silicon),germanium, silicon germanium, silicon carbide, gallium arsenide,aluminum gallium arsenide, indium phosphide, gallium nitride, and anorganic semiconductor), and the second semiconductor material can be anoxide semiconductor. A transistor using a material other than an oxidesemiconductor, such as single crystal silicon, can operate at high speedeasily. In contrast, a transistor using an oxide semiconductor anddescribed in the above embodiment as an example has excellentsubthreshold characteristics and a minute structure. Furthermore, thetransistor can operate at a high speed because of its high switchingspeed and has low leakage current because of its low off-state current.

The transistor 2200 may be either an n-channel transistor or a p-channeltransistor, and an appropriate transistor may be used in accordance witha circuit. Furthermore, the specific structure of the semiconductordevice, such as the material or the structure used for the semiconductordevice, is not necessarily limited to those described here except forthe use of the transistor of one embodiment of the present inventionwhich uses an oxide semiconductor.

FIG. 27A illustrates a structure in which the transistor 2100 isprovided over the transistor 2200 with an insulator 2201 and aninsulator 2207 provided therebetween. A plurality of wirings 2202 areprovided between the transistor 2200 and the transistor 2100.Furthermore, wirings and electrodes provided over and under theinsulators are electrically connected to each other through a pluralityof plugs 2203 embedded in the insulators. An insulator 2204 covering thetransistor 2100 and a wiring 2205 over the insulator 2204 are provided.

The stack of the two kinds of transistors reduces the area occupied bythe circuit, allowing a plurality of circuits to be highly integrated.

Here, in the case where a silicon-based semiconductor material is usedfor the transistor 2200 provided in a lower portion, hydrogen in aninsulator provided in the vicinity of the semiconductor film of thetransistor 2200 terminates dangling bonds of silicon; accordingly, thereliability of the transistor 2200 can be improved. Meanwhile, in thecase where an oxide semiconductor is used for the transistor 2100provided in an upper portion, hydrogen in an insulator provided in thevicinity of the semiconductor film of the transistor 2100 becomes afactor of generating carriers in the oxide semiconductor; thus, thereliability of the transistor 2100 might be decreased. Therefore, in thecase where the transistor 2100 using an oxide semiconductor is providedover the transistor 2200 using a silicon-based semiconductor material,it is particularly effective that the insulator 2207 having a functionof preventing diffusion of hydrogen is provided between the transistors2100 and 2200. The insulator 2207 makes hydrogen remain in the lowerportion, thereby improving the reliability of the transistor 2200. Inaddition, since the insulator 2207 suppresses diffusion of hydrogen fromthe lower portion to the upper portion, the reliability of thetransistor 2100 can also be improved.

The insulator 2207 can be, for example, formed using aluminum oxide,aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide,yttrium oxynitride, hafnium oxide, hafnium oxynitride, oryttria-stabilized zirconia (YSZ).

Furthermore, a blocking film having a function of preventing diffusionof hydrogen is preferably formed over the transistor 2100 to cover thetransistor 2100 including an oxide semiconductor film. For the blockingfilm, a material that is similar to that of the insulator 2207 can beused, and in particular, an aluminum oxide film is preferably used. Thealuminum oxide film has a high shielding (blocking) effect of preventingpenetration of both oxygen and impurities such as hydrogen and moisture.Thus, by using the aluminum oxide film as the blocking film covering thetransistor 2100, release of oxygen from the oxide semiconductor filmincluded in the transistor 2100 can be prevented and entry of water andhydrogen into the oxide semiconductor film can be prevented. Note thatas the block film, the insulator 2204 having a stacked-layer structuremay be used, or the block film may be provided under the insulator 2204.

Note that the transistor 2200 can be a transistor of various typeswithout being limited to a planar type transistor. For example, thetransistor 2200 can be a fin-type transistor, a tri-gate transistor, orthe like. An example of a cross-sectional view in this case is shown inFIG. 27D. An insulator 2212 is provided over a semiconductor substrate2211. The semiconductor substrate 2211 includes a projecting portionwith a thin tip (also referred to a fin). Note that an insulator may beprovided over the projecting portion. The insulator functions as a maskfor preventing the semiconductor substrate 2211 from being etched whenthe projecting portion is formed. The projecting portion does notnecessarily have the thin tip; a projecting portion with a cuboid-likeprojecting portion and a projecting portion with a thick tip arepermitted, for example. A gate insulator 2214 is provided over theprojecting portion of the semiconductor substrate 2211, and a gateelectrode 2213 is provided over the gate insulator 2214. Source anddrain regions 2215 are formed in the semiconductor substrate 2211. Notethat here is shown an example in which the semiconductor substrate 2211includes the projecting portion; however, a semiconductor device of oneembodiment of the present invention is not limited thereto. For example,a semiconductor region having a projecting portion may be formed byprocessing an SOI substrate.

<Circuit Configuration Example>

In the above structure, electrodes of the transistor 2100 and thetransistor 2200 can be connected as appropriate; thus, a variety ofcircuits can be formed. Examples of circuit configurations which can beachieved by using a semiconductor device of one embodiment of thepresent invention are shown below.

<CMOS Inverter Circuit>

A circuit diagram in FIG. 27B shows a configuration of a CMOS inverterin which the p-channel transistor 2200 and the n-channel transistor 2100are connected to each other in series and in which gates of them areconnected to each other.

<CMOS Analog Switch>

A circuit diagram in FIG. 27C shows a configuration in which sources ofthe transistors 2100 and 2200 are connected to each other and drains ofthe transistors 2100 and 2200 are connected to each other. With such aconfiguration, the transistors can function as a CMOS analog switch.

<Memory Device Example>

An example of a semiconductor device (memory device) which includes thetransistor of one embodiment of the present invention, which can retainstored data even when not powered, and which has an unlimited number ofwrite cycles is shown in FIGS. 28A to 28C.

The semiconductor device illustrated in FIG. 28A includes a transistor3200 using a first semiconductor material, a transistor 3300 using asecond semiconductor material, and a capacitor 3400. Note that any ofthe transistors in Embodiments 1 and 2 can be used as the transistor3300.

FIG. 28B is a cross-sectional view of the semiconductor deviceillustrated in FIG. 28A. The semiconductor device in the cross-sectionalview has a structure in which the transistor 3300 is provided with aback gate; however, a structure without a back gate may be employed.

The transistor 3300 is a transistor in which a channel is formed in asemiconductor layer including an oxide semiconductor. Since theoff-state current of the transistor 3300 is low, stored data can beretained for a long period. In other words, power consumption can besufficiently reduced because a semiconductor memory device in whichrefresh operation is unnecessary or the frequency of refresh operationis extremely low can be provided.

In FIG. 28A, a first wiring 3001 is electrically connected to a sourceelectrode of the transistor 3200. A second wiring 3002 is electricallyconnected to a drain electrode of the transistor 3200. A third wiring3003 is electrically connected to one of a source electrode and a drainelectrode of the transistor 3300. A fourth wiring 3004 is electricallyconnected to a gate electrode of the transistor 3300. A gate electrodeof the transistor 3200 is electrically connected to the other of thesource electrode and the drain electrode of the transistor 3300 and afirst terminal of the capacitor 3400. A fifth wiring 3005 iselectrically connected to a second terminal of the capacitor 3400.

The semiconductor device in FIG. 28A has a feature that the potential ofthe gate electrode of the transistor 3200 can be retained, and thusenables writing, retaining, and reading of data as follows.

Writing and retaining of data are described. First, the potential of thefourth wiring 3004 is set to a potential at which the transistor 3300 isturned on, so that the transistor 3300 is turned on. Accordingly, thepotential of the third wiring 3003 is supplied to the gate electrode ofthe transistor 3200 and the capacitor 3400. That is, a predeterminedcharge is supplied to the gate electrode of the transistor 3200(writing). Here, one of two kinds of charges providing differentpotential levels (hereinafter referred to as a low-level charge and ahigh-level charge) is supplied. After that, the potential of the fourthwiring 3004 is set to a potential at which the transistor 3300 is turnedoff, so that the transistor 3300 is turned off. Thus, the chargesupplied to the gate electrode of the transistor 3200 is held(retaining).

Since the off-state current of the transistor 3300 is extremely low, thecharge of the gate of the transistor 3200 is retained for a long time.

Next, reading of data is described. An appropriate potential (a readingpotential) is supplied to the fifth wiring 3005 while a predeterminedpotential (a constant potential) is supplied to the first wiring 3001,whereby the potential of the second wiring 3002 varies depending on theamount of charge retained in the gate of the transistor 3200. This isbecause in the case of using an n-channel transistor as the transistor3200, an apparent threshold voltage V_(th) _(_) _(H) at the time whenthe high-level charge is given to the gate electrode of the transistor3200 is lower than an apparent threshold voltage V_(th) _(_) _(L) at thetime when the low-level charge is given to the gate electrode of thetransistor 3200. Here, an apparent threshold voltage refers to thepotential of the fifth wiring 3005 which is needed to turn on thetransistor 3200. Thus, the potential of the fifth wiring 3005 is set toa potential V₀ which is between V_(th) _(_) _(H) and V_(th) _(_) _(L),whereby charge supplied to the gate of the transistor 3200 can bedetermined. For example, in the case where the high-level charge issupplied to the gate electrode of the transistor 3200 in writing and thepotential of the fifth wiring 3005 is V₀ (>V_(th) _(_) _(H)), thetransistor 3200 is turned on. In the case where the low-level charge issupplied to the gate electrode of the transistor 3200 in writing, evenwhen the potential of the fifth wiring 3005 is V₀ (<V_(th) _(_) _(L)),the transistor 3200 remains off. Thus, the data retained in the gateelectrode of the transistor 3200 can be read by determining thepotential of the second wiring 3002.

Note that in the case where memory cells are arrayed to be used, it isnecessary that only data of a desired memory cell be able to be read.For example, the fifth wiring 3005 of memory cells from which data isnot read may be supplied with a potential at which the transistor 3200is turned off regardless of the state of the gate electrode, that is, apotential lower than V_(th) _(_) _(H), whereby only data of a desiredmemory cell can be read. Alternatively, the fifth wiring 3005 of thememory cells from which data is not read may be supplied with apotential at which the transistor 3200 is turned on regardless of thestate of the gate, that is, a potential higher than V_(th) _(_) _(L),whereby only data of a desired memory cell can be read.

The semiconductor device illustrated in FIG. 28C is different from thesemiconductor device illustrated in FIG. 28A in that the transistor 3200is not provided. Also in this case, writing and retaining operation ofdata can be performed in a manner similar to the semiconductor deviceillustrated in FIG. 28A.

Next, reading of data is described. When the transistor 3300 is turnedon, the third wiring 3003 which is in a floating state and the capacitor3400 are electrically connected to each other, and the charge isredistributed between the third wiring 3003 and the capacitor 3400. As aresult, the potential of the third wiring 3003 is changed. The amount ofchange in the potential of the third wiring 3003 varies depending on thepotential of a first terminal of the capacitor 3400 (or the chargeaccumulated in the capacitor 3400).

For example, the potential of the third wiring 3003 after the chargeredistribution is (C_(B)×V_(B0)+C×V)/(C_(B)+C), where Vis the potentialof the first terminal of the capacitor 3400, C is the capacitance of thecapacitor 3400, C_(B) is the capacitance component of the third wiring3003, and V_(B0) is the potential of the third wiring 3003 before thecharge redistribution. Thus, it can be found that, assuming that thememory cell is in either of two states in which the potential of thefirst terminal of the capacitor 3400 is V₁ and V₀ (V₁>V₀), the potentialof the third wiring 3003 in the case of retaining the potential V₁(=(C_(B)×V_(B0)+C×V₁)/(C_(B)+C)) is higher than the potential of thethird wiring 3003 in the case of retaining the potential V₀(=(C_(B)×V_(B0)+C×V₀)/(C_(B)+C)).

Then, by comparing the potential of the third wiring 3003 with apredetermined potential, data can be read.

In this case, a transistor including the first semiconductor materialmay be used for a driver circuit for driving a memory cell, and atransistor including the second semiconductor material may be stackedover the driver circuit as the transistor 3300.

When including a transistor in which a channel formation region isformed using an oxide semiconductor and which has an extremely lowoff-state current, the semiconductor device described in this embodimentcan retain stored data for an extremely long time. In other words,refresh operation becomes unnecessary or the frequency of the refreshoperation can be extremely low, which leads to a sufficient reduction inpower consumption. Moreover, stored data can be retained for a long timeeven when power is not supplied (note that a potential is preferablyfixed).

Further, in the semiconductor device described in this embodiment, highvoltage is not needed for writing data and there is no problem ofdeterioration of elements. Unlike in a conventional nonvolatile memory,for example, it is not necessary to inject and extract electrons intoand from a floating gate; thus, a problem such as deterioration of agate insulating layer is not caused. That is, the semiconductor deviceof the disclosed invention does not have a limit on the number of timesdata can be rewritten, which is a problem of a conventional nonvolatilememory, and the reliability thereof is drastically improved.Furthermore, data is written depending on the state of the transistor(on or off), whereby high-speed operation can be easily achieved.

Note that in this specification and the like, it might be possible forthose skilled in the art to constitute one embodiment of the inventioneven when portions to which all the terminals of an active element(e.g., a transistor or a diode), a passive element (e.g., a capacitor ora resistor), or the like are connected are not specified. In otherwords, one embodiment of the invention can be clear even when connectionportions are not specified. Further, in the case where a connectionportion is disclosed in this specification and the like, it can bedetermined that one embodiment of the invention in which a connectionportion is not specified is disclosed in this specification and thelike, in some cases. In particular, in the case where the number ofportions to which the terminal is connected might be plural, it is notnecessary to specify the portions to which the terminal is connected.Therefore, it might be possible to constitute one embodiment of theinvention by specifying only portions to which some of terminals of anactive element (e.g., a transistor or a diode), a passive element (e.g.,a capacitor or a resistor), or the like are connected.

Note that in this specification and the like, it might be possible forthose skilled in the art to specify the invention when at least theconnection portion of a circuit is specified. Alternatively, it might bepossible for those skilled in the art to specify the invention when atleast a function of a circuit is specified. In other words, when afunction of a circuit is specified, one embodiment of the invention canbe clear. Furthermore, it can be determined that one embodiment of theinvention whose function is specified is disclosed in this specificationand the like. Therefore, when a connection portion of a circuit isspecified, the circuit is disclosed as one embodiment of the inventioneven when a function is not specified, and one embodiment of theinvention can be constituted. Alternatively, when a function of acircuit is specified, the circuit is disclosed as one embodiment of theinvention even when a connection portion is not specified, and oneembodiment of the invention can be constituted.

Note that in this specification and the like, in a diagram or a textdescribed in one embodiment, it is possible to take out part of thediagram or the text and constitute an embodiment of the invention. Thus,in the case where a diagram or a text related to a certain portion isdescribed, the context taken out from part of the diagram or the text isalso disclosed as one embodiment of the invention, and one embodiment ofthe invention can be constituted. Therefore, for example, in a diagramor text in which one or more active elements (e.g., transistors ordiodes), wirings, passive elements (e.g., capacitors or resistors),conductive layers, insulating layers, semiconductor layers, organicmaterials, inorganic materials, components, devices, operating methods,manufacturing methods, or the like are described, part of the diagram orthe text is taken out, and one embodiment of the invention can beconstituted. For example, from a circuit diagram in which N circuitelements (e.g., transistors or capacitors; N is an integer) areprovided, it is possible to constitute one embodiment of the inventionby taking out M circuit elements (e.g., transistors or capacitors; M isan integer, where M<N). As another example, it is possible to constituteone embodiment of the invention by taking out M layers (M is an integer,where M<N) from a cross-sectional view in which N layers (Nis aninteger) are provided. As another example, it is possible to constituteone embodiment of the invention by taking out M elements (M is aninteger, where M<N) from a flow chart in which N elements (N is aninteger) are provided.

<Imaging Device>

An imaging device of one embodiment of the present invention isdescribed below.

FIG. 29A is a plan view illustrating an example of an imaging device 200of one embodiment of the present invention. The imaging device 200includes a pixel portion 210 and peripheral circuits for driving thepixel portion 210 (a peripheral circuit 260, a peripheral circuit 270, aperipheral circuit 280, and a peripheral circuit 290). The pixel portion210 includes a plurality of pixels 211 arranged in a matrix with p rowsand q columns (p and q are each a natural number greater than or equalto 2). The peripheral circuit 260, the peripheral circuit 270, theperipheral circuit 280, and the peripheral circuit 290 are eachconnected to a plurality of pixels 211, and a signal for driving theplurality of pixels 211 is supplied. In this specification and the like,in some cases, “a peripheral circuit” or “a driver circuit” indicatesall of the peripheral circuits 260, 270, 280, and 290. For example, theperipheral circuit 260 can be regarded as part of the peripheralcircuit.

The imaging device 200 preferably includes a light source 291. The lightsource 291 can emit detection light P1.

The peripheral circuit includes at least one of a logic circuit, aswitch, a buffer, an amplifier circuit, and a converter circuit. Theperipheral circuit may be provided over a substrate where the pixelportion 210 is formed. Part or the whole of the peripheral circuit maybe mounted using a semiconductor device such as an IC. Note that as theperipheral circuit, one or more of the peripheral circuits 260, 270,280, and 290 may be omitted.

As illustrated in FIG. 29B, the pixels 211 may be provided to beinclined in the pixel portion 210 included in the imaging device 200.When the pixels 211 are obliquely arranged, the distance between pixels(pitch) can be shortened in the row direction and the column direction.Accordingly, the quality of an image taken with the imaging device 200can be improved.

<Configuration Example 1 of Pixel>

The pixel 211 included in the imaging device 200 is formed with aplurality of subpixels 212, and each subpixel 212 is combined with afilter which transmits light with a specific wavelength band (colorfilter), whereby data for achieving color image display can be obtained.

FIG. 30A is a plan view showing an example of the pixel 211 with which acolor image is obtained. The pixel 211 illustrated in FIG. 30A includesa subpixel 212 provided with a color filter transmitting light with ared (R) wavelength band (also referred to as a subpixel 212R), asubpixel 212 provided with a color filter transmitting light with agreen (G) wavelength band (also referred to as a subpixel 212G), and asubpixel 212 provided with a color filter transmitting light with a blue(B) wavelength band (also referred to as a subpixel 212B). The subpixel212 can function as a photosensor.

The subpixel 212 (the subpixel 212R, the subpixel 212G, and the subpixel212B) is electrically connected to a wiring 231, a wiring 247, a wiring248, a wiring 249, and a wiring 250. In addition, the subpixel 212R, thesubpixel 212G, and the subpixel 212B are connected to respective wirings253 which are independent from one another. In this specification andthe like, for example, the wiring 248 and the wiring 249 that areconnected to the pixel 211 in the n-th row (n is an integer greater thanor equal to 1 and less than or equal to p) are referred to as a wiring248[n] and a wiring 249[n]. For example, the wiring 253 connected to thepixel 211 in the m-th column (m is an integer greater than or equal to 1and less than or equal to q) is referred to as a wiring 253[m]. Notethat in FIG. 30A, the wirings 253 connected to the subpixel 212R, thesubpixel 212G, and the subpixel 212B in the pixel 211 in the m-th columnare referred to as a wiring 253[m]R, a wiring 253[m]G, and a wiring253[m]B. The subpixels 212 are electrically connected to the peripheralcircuit through the above wirings.

The imaging device 200 has a structure in which the subpixel 212 iselectrically connected to the subpixel 212 in an adjacent pixel 211which is provided with a color filter transmitting light with the samewavelength band as the subpixel 212, via a switch. FIG. 30B shows aconnection example of the subpixels 212: the subpixel 212 in the pixel211 arranged in an n-th row and an m-th column and the subpixel 212 inthe adjacent pixel 211 arranged in an (n+1)-th row and the m-th column.In FIG. 30B, the subpixel 212R arranged in the n-th row and the m-thcolumn and the subpixel 212R arranged in the (n+1)-th row and the m-thcolumn are connected to each other via a switch 201. The subpixel 212Garranged in the n-th row and the m-th column and the subpixel 212Garranged in the (n+1)-th row and the m-th column are connected to eachother via a switch 202. The subpixel 212B arranged in the n-th row andthe m-th column and the subpixel 212B arranged in the (n+1)-th row andthe m-th column are connected to each other via a switch 203.

The color filter used in the subpixel 212 is not limited to red (R),green (G), and blue (B) color filters, and color filters that transmitlight of cyan (C), yellow (Y), and magenta (M) may be used. By provisionof the subpixels 212 that sense light with three different wavelengthbands in one pixel 211, a full-color image can be obtained.

The pixel 211 including the subpixel 212 provided with a color filtertransmitting yellow (Y) light may be provided, in addition to thesubpixels 212 provided with the color filters transmitting red (R),green (G), and blue (B) light. The pixel 211 including the subpixel 212provided with a color filter transmitting blue (B) light may beprovided, in addition to the subpixels 212 provided with the colorfilters transmitting cyan (C), yellow (Y), and magenta (M) light. Whenthe subpixels 212 sensing light with four different wavelength bands areprovided in one pixel 211, the reproducibility of colors of an obtainedimage can be increased.

For example, in FIG. 30A, in regard to the subpixel 212 sensing a redwavelength band, the subpixel 212 sensing a green wavelength band, andthe subpixel 212 sensing a blue wavelength band, the pixel number ratio(or the light receiving area ratio) thereof is not necessarily 1:1:1.For example, the Bayer arrangement in which the pixel number ratio (thelight receiving area ratio) is set at red: green: blue=1:2:1 may beemployed. Alternatively, the pixel number ratio (the light receivingarea ratio) of red and green to blue may be 1:6:1.

Although the number of subpixels 212 provided in the pixel 211 may beone, two or more subpixels are preferably provided. For example, whentwo or more subpixels 212 sensing the same wavelength band are provided,the redundancy is increased, and the reliability of the imaging device200 can be increased.

When an infrared (IR) filter that transmits infrared light and absorbsor reflects visible light is used as the filter, the imaging device 200that senses infrared light can be achieved.

Furthermore, when a neutral density (ND) filter (dark filter) is used,output saturation which occurs when a large amount of light enters aphotoelectric conversion element (light-receiving element) can beprevented. With a combination of ND filters with different dimmingcapabilities, the dynamic range of the imaging device can be increased.

Besides the above-described filter, the pixel 211 may be provided with alens. An arrangement example of the pixel 211, a filter 254, and a lens255 is described with cross-sectional views in FIGS. 31A and 31B. Withthe lens 255, the photoelectric conversion element can receive incidentlight efficiently. Specifically, as illustrated in FIG. 31A, light 256enters a photoelectric conversion element 220 through the lens 255, thefilter 254 (a filter 254R, a filter 254G, and a filter 254B), a pixelcircuit 230, and the like which are provided in the pixel 211.

However, as indicated by a region surrounded with dashed-dotted lines,part of the light 256 indicated by arrows might be blocked by somewirings 257. Thus, a preferable structure is that the lens 255 and thefilter 254 are provided on the photoelectric conversion element 220side, so that the photoelectric conversion element 220 can efficientlyreceive the light 256 as illustrated in FIG. 31B. When the light 256enters the photoelectric conversion element 220 from the photoelectricconversion element 220 side, the imaging device 200 with highsensitivity can be provided.

As the photoelectric conversion element 220 illustrated in FIGS. 31A and31B, a photoelectric conversion element in which a p-n junction or ap-i-n junction is formed may be used.

The photoelectric conversion element 220 may be formed using a substancethat has a function of absorbing a radiation and generating electriccharges. Examples of the substance that has a function of absorbing aradiation and generating electric charges include selenium, lead iodide,mercury iodide, gallium arsenide, cadmium telluride, and cadmium zincalloy.

For example, when selenium is used for the photoelectric conversionelement 220, the photoelectric conversion element 220 can have a lightabsorption coefficient in a wide wavelength range, such as visiblelight, ultraviolet light, infrared light, X-rays, and gamma rays.

One pixel 211 included in the imaging device 200 may include thesubpixel 212 with a first filter in addition to the subpixel 212illustrated in FIGS. 31A and 31B.

<Configuration Example 2 of Pixel>

An example of a pixel including a transistor using silicon and atransistor using an oxide semiconductor is described below.

FIGS. 32A and 32B are each a cross-sectional view of an element includedin an imaging device.

The imaging device illustrated in FIG. 32A includes a transistor 351including silicon over a silicon substrate 300, transistors 352 and 353which include an oxide semiconductor and are stacked over the transistor351, and a photodiode 360 provided in a silicon substrate 300 andincluding an anode 361 and a cathode 362. The transistors and thephotodiode 360 are electrically connected to various plugs 370 andwirings 371. In addition, an anode 361 of the photodiode 360 iselectrically connected to the plug 370 through a low-resistance region363.

The imaging device includes a layer 310 including the transistor 351provided on the silicon substrate 300 and the photodiode 360 provided inthe silicon substrate 300, a layer 320 which is in contact with thelayer 310 and includes the wirings 371, a layer 330 which is in contactwith the layer 320 and includes the transistors 352 and 353, and a layer340 which is in contact with the layer 330 and includes a wiring 372 anda wiring 373.

Note that in the example of cross-sectional view in FIG. 32A, alight-receiving surface of the photodiode 360 is provided on the sideopposite to a surface of the silicon substrate 300 where the transistor351 is formed. With the structure, an optical path can be obtainedwithout the influence by the transistors or wirings, and therefore, apixel with a high aperture ratio can be formed. Thus, a pixel with ahigh aperture ratio can be formed. Note that the light-receiving surfaceof the photodiode 360 can be the same as the surface where thetransistor 351 is formed.

In the case where a pixel is formed with use of only transistors usingan oxide semiconductor, the layer 310 may include the transistor usingan oxide semiconductor. Alternatively, the layer 310 may be omitted, andthe pixel may include only transistors using an oxide semiconductor.

In addition, in the cross-sectional view in FIG. 32A, the photodiode 360in the layer 310 and the transistor in the layer 330 can be formed so asto overlap with each other. Thus, the degree of integration of pixelscan be increased. In other words, the resolution of the imaging devicecan be increased.

An imaging device shown in FIG. 32B includes a photodiode 365 in thelayer 340 and over the transistor. In FIG. 32B, the layer 310 includes atransistor 350 and the transistor 351 using silicon, the layer 320includes the wiring 371, the layer 330 includes the transistor 352 andthe transistor 353 using an oxide semiconductor layer, and the layer 340includes the photodiode 365. The photodiode 365 includes a semiconductorlayer 366, a semiconductor layer 367, and a semiconductor layer 368, andis electrically connected to the wiring 373 and a wiring 374 through theplug 370.

The element structure shown in FIG. 32B can increase the aperture ratio.

Alternatively, a PIN diode element formed using an amorphous siliconfilm, a microcrystalline silicon film, or the like may be used as thephotodiode 365. In the photodiode 365, an n-type semiconductor layer368, an i-type semiconductor layer 367, and a p-type semiconductor layer366 are stacked in this order. The i-type semiconductor layer 367 ispreferably formed using amorphous silicon. The p-type semiconductorlayer 366 and the n-type semiconductor layer 368 can each be formedusing amorphous silicon, microcrystalline silicon, or the like whichincludes a dopant imparting the corresponding conductivity type. Aphotodiode in which the photodiode 365 is formed using amorphous siliconhas high sensitivity in a visible light wavelength region, and thereforecan easily sense weak visible light.

This embodiment can be combined as appropriate with any of the otherembodiments and examples in this specification.

Embodiment 5 <RF Tag>

In this embodiment, an RF tag that includes the transistor described inthe above embodiments or the memory device described in the aboveembodiment is described with reference to FIG. 33.

The RF tag of this embodiment includes a memory circuit, storesnecessary data in the memory circuit, and transmits and receives datato/from the outside by using contactless means, for example, wirelesscommunication. With these features, the RF tag can be used for anindividual authentication system in which an object or the like isrecognized by reading the individual information, for example. Note thatthe RF tag is required to have extremely high reliability in order to beused for this purpose.

A configuration of the RF tag will be described with reference to FIG.33. FIG. 33 is a block diagram illustrating a configuration example ofan RF tag.

As shown in FIG. 33, an RF tag 800 includes an antenna 804 whichreceives a radio signal 803 that is transmitted from an antenna 802connected to a communication device 801 (also referred to as aninterrogator, a reader/writer, or the like). The RF tag 800 includes arectifier circuit 805, a constant voltage circuit 806, a demodulationcircuit 807, a modulation circuit 808, a logic circuit 809, a memorycircuit 810, and a ROM 811. A transistor having a rectifying functionincluded in the demodulation circuit 807 may be formed using a materialwhich enables a reverse current to be low enough, for example, an oxidesemiconductor. This can suppress the phenomenon of a rectifying functionbecoming weaker due to generation of a reverse current and preventsaturation of the output from the demodulation circuit. In other words,the input to the demodulation circuit and the output from thedemodulation circuit can have a relation closer to a linear relation.Note that data transmission methods are roughly classified into thefollowing three methods: an electromagnetic coupling method in which apair of coils is provided so as to face each other and communicates witheach other by mutual induction, an electromagnetic induction method inwhich communication is performed using an induction field, and a radiowave method in which communication is performed using a radio wave. Anyof these methods can be used in the RF tag 800 described in thisembodiment.

Next, the structure of each circuit will be described. The antenna 804exchanges the radio signal 803 with the antenna 802 which is connectedto the communication device 801. The rectifier circuit 805 generates aninput potential by rectification, for example, half-wave voltage doublerrectification of an input alternating signal generated by reception of aradio signal at the antenna 804 and smoothing of the rectified signalwith a capacitor provided in a later stage in the rectifier circuit 805.Note that a limiter circuit may be provided on an input side or anoutput side of the rectifier circuit 805. The limiter circuit controlselectric power so that electric power which is higher than or equal tocertain electric power is not input to a circuit in a later stage if theamplitude of the input alternating signal is high and an internalgeneration voltage is high.

The constant voltage circuit 806 generates a stable power supply voltagefrom an input potential and supplies it to each circuit. Note that theconstant voltage circuit 806 may include a reset signal generationcircuit. The reset signal generation circuit is a circuit whichgenerates a reset signal of the logic circuit 809 by utilizing rise ofthe stable power supply voltage.

The demodulation circuit 807 demodulates the input alternating signal byenvelope detection and generates the demodulated signal. Further, themodulation circuit 808 performs modulation in accordance with data to beoutput from the antenna 804.

The logic circuit 809 analyzes and processes the demodulated signal. Thememory circuit 810 holds the input data and includes a row decoder, acolumn decoder, a memory region, and the like. Further, the ROM 811stores an identification number (ID) or the like and outputs it inaccordance with processing.

Note that the decision whether each circuit described above is providedor not can be made as appropriate as needed.

Here, the memory circuit described in the above embodiment can be usedas the memory circuit 810. Since the memory circuit of one embodiment ofthe present invention can retain data even when not powered, the memorycircuit can be favorably used for an RF tag. Furthermore, the memorycircuit of one embodiment of the present invention needs power (voltage)needed for data writing significantly lower than that needed in aconventional nonvolatile memory; thus, it is possible to prevent adifference between the maximum communication range in data reading andthat in data writing. In addition, it is possible to suppressmalfunction or incorrect writing which is caused by power shortage indata writing.

Since the memory circuit of one embodiment of the present invention canbe used as a nonvolatile memory, it can also be used as the ROM 811. Inthis case, it is preferable that a manufacturer separately prepare acommand for writing data to the ROM 811 so that a user cannot rewritedata freely. Since the manufacturer gives identification numbers beforeshipment and then starts shipment of products, instead of puttingidentification numbers to all the manufactured RF tags, it is possibleto put identification numbers to only good products to be shipped. Thus,the identification numbers of the shipped products are in series andcustomer management corresponding to the shipped products is easilyperformed.

This embodiment can be combined as appropriate with any of the otherembodiments and examples in this specification.

Embodiment 6

In this embodiment, a CPU that includes the memory device described inthe above embodiment is described.

FIG. 34 is a block diagram illustrating a configuration example of a CPUat least partly including any of the transistors described in the aboveembodiments as a component.

<Circuit Diagram of CPU>

The CPU illustrated in FIG. 34 includes, over a substrate 1190, anarithmetic logic unit (ALU) 1191, an ALU controller 1192, an instructiondecoder 1193, an interrupt controller 1194, a timing controller 1195, aregister 1196, a register controller 1197, a bus interface 1198, arewritable ROM 1199, and a ROM interface 1189. A semiconductorsubstrate, an SOI substrate, a glass substrate, or the like is used asthe substrate 1190. The rewritable ROM 1199 and the ROM interface 1189may be provided over a separate chip. Needless to say, the CPU in FIG.34 is just an example in which the configuration is simplified, and anactual CPU may have a variety of configurations depending on theapplication. For example, the CPU may have the following configuration:a structure including the CPU illustrated in FIG. 34 or an arithmeticcircuit is considered as one core; a plurality of the cores areincluded; and the cores operate in parallel. The number of bits that theCPU can process in an internal arithmetic circuit or in a data bus canbe 8, 16, 32, or 64, for example.

An instruction that is input to the CPU through the bus interface 1198is input to the instruction decoder 1193 and decoded therein, and then,input to the ALU controller 1192, the interrupt controller 1194, theregister controller 1197, and the timing controller 1195.

The ALU controller 1192, the interrupt controller 1194, the registercontroller 1197, and the timing controller 1195 conduct various controlsin accordance with the decoded instruction. Specifically, the ALUcontroller 1192 generates signals for controlling the operation of theALU 1191. While the CPU is executing a program, the interrupt controller1194 judges an interrupt request from an external input/output device ora peripheral circuit on the basis of its priority or a mask state, andprocesses the request. The register controller 1197 generates an addressof the register 1196, and reads/writes data from/to the register 1196 inaccordance with the state of the CPU.

The timing controller 1195 generates signals for controlling operationtimings of the ALU 1191, the ALU controller 1192, the instructiondecoder 1193, the interrupt controller 1194, and the register controller1197. For example, the timing controller 1195 includes an internal clockgenerator for generating an internal clock signal based on a referenceclock signal, and supplies the internal clock signal to the abovecircuits.

In the CPU illustrated in FIG. 34, a memory cell is provided in theregister 1196. For the memory cell of the register 1196, any of thetransistors described in Embodiments 1 and 2 can be used.

In the CPU illustrated in FIG. 34, the register controller 1197 selectsoperation of retaining data in the register 1196 in accordance with aninstruction from the ALU 1191. That is, the register controller 1197selects whether data is retained by a flip-flop or by a capacitor in thememory cell included in the register 1196. When data retaining by theflip-flop is selected, a power supply voltage is supplied to the memorycell in the register 1196. When data retaining by the capacitor isselected, the data is rewritten in the capacitor, and supply of powersupply voltage to the memory cell in the register 1196 can be stopped.

<Memory Circuit>

FIG. 35 is an example of a circuit diagram of a memory element that canbe used as the register 1196. A memory element 1200 includes a circuit1201 in which stored data is volatile when power supply is stopped, acircuit 1202 in which stored data is nonvolatile even when power supplyis stopped, a switch 1203, a switch 1204, a logic element 1206, acapacitor 1207, and a circuit 1220 having a selecting function. Thecircuit 1202 includes a capacitor 1208, a transistor 1209, and atransistor 1210. Note that the memory element 1200 may further includeanother element such as a diode, a resistor, or an inductor, as needed.

Here, the memory device described in the above embodiment can be used asthe circuit 1202. When supply of a power supply voltage to the memoryelement 1200 is stopped, a ground potential (0 V) or a potential atwhich the transistor 1209 in the circuit 1202 is turned off continues tobe input to a gate of the transistor 1209. For example, a first gate ofthe transistor 1209 is grounded through a load such as a resistor.

Shown here is an example in which the switch 1203 is a transistor 1213having one conductivity type (e.g., an n-channel transistor) and theswitch 1204 is a transistor 1214 having a conductivity type opposite tothe one conductivity type (e.g., a p-channel transistor). A firstterminal of the switch 1203 corresponds to one of a source and a drainof the transistor 1213, a second terminal of the switch 1203 correspondsto the other of the source and the drain of the transistor 1213, andconduction or non-conduction between the first terminal and the secondterminal of the switch 1203 (i.e., the on/off state of the transistor1213) is selected by a control signal RD input to a gate of thetransistor 1213. A first terminal of the switch 1204 corresponds to oneof a source and a drain of the transistor 1214, a second terminal of theswitch 1204 corresponds to the other of the source and the drain of thetransistor 1214, and conduction or non-conduction between the firstterminal and the second terminal of the switch 1204 (i.e., the on/offstate of the transistor 1214) is selected by the control signal RD inputto a gate of the transistor 1214.

One of a source and a drain of the transistor 1209 is electricallyconnected to one of a pair of electrodes of the capacitor 1208 and agate of the transistor 1210. Here, the connection portion is referred toas a node M2. One of a source and a drain of the transistor 1210 iselectrically connected to a line which can supply a low power supplypotential (e.g., a GND line), and the other thereof is electricallyconnected to the first terminal of the switch 1203 (the one of thesource and the drain of the transistor 1213). The second terminal of theswitch 1203 (the other of the source and the drain of the transistor1213) is electrically connected to the first terminal of the switch 1204(the one of the source and the drain of the transistor 1214). The secondterminal of the switch 1204 (the other of the source and the drain ofthe transistor 1214) is electrically connected to a line which cansupply a power supply potential VDD. The second terminal of the switch1203 (the other of the source and the drain of the transistor 1213), thefirst terminal of the switch 1204 (the one of the source and the drainof the transistor 1214), an input terminal of the logic element 1206,and one of a pair of electrodes of the capacitor 1207 are electricallyconnected to each other. Here, the connection portion is referred to asa node M1. The other of the pair of electrodes of the capacitor 1207 canbe supplied with a constant potential. For example, the other of thepair of electrodes of the capacitor 1207 can be supplied with a lowpower supply potential (e.g., GND) or a high power supply potential(e.g., VDD). The other of the pair of electrodes of the capacitor 1207is electrically connected to the line which can supply a low powersupply potential (e.g., a GND line). The other of the pair of electrodesof the capacitor 1208 can be supplied with a constant potential. Forexample, the other of the pair of electrodes of the capacitor 1208 canbe supplied with a low power supply potential (e.g., GND) or a highpower supply potential (e.g., VDD). The other of the pair of electrodesof the capacitor 1208 is electrically connected to the line which cansupply a low power supply potential (e.g., a GND line).

The capacitor 1207 and the capacitor 1208 are not necessarily providedas long as the parasitic capacitance of the transistor, the wiring, orthe like is actively utilized.

A control signal WE is input to the first gate (first gate electrode) ofthe transistor 1209. As for each of the switch 1203 and the switch 1204,a conduction state or a non-conduction state between the first terminaland the second terminal is selected by the control signal RD which isdifferent from the control signal WE. When the first terminal and thesecond terminal of one of the switches are in the conduction state, thefirst terminal and the second terminal of the other of the switches arein the non-conduction state.

Note that the transistor 1209 in FIG. 35 has a structure with a secondgate (second gate electrode: back gate). The control signal WE can beinput to the first gate and the control signal WE2 can be input to thesecond gate. The control signal WE2 is a signal having a constantpotential. As the constant potential, for example, a ground potentialGND or a potential lower than a source potential of the transistor 1209is selected. The control signal WE2 is a potential signal forcontrolling the threshold voltage of the transistor 1209, and a currentwhen a gate voltage VG is 0 V can be further reduced. The control signalWE2 may be a signal having the same potential as that of the controlsignal WE. Note that as the transistor 1209, a transistor without asecond gate may be used.

A signal corresponding to data retained in the circuit 1201 is input tothe other of the source and the drain of the transistor 1209. FIG. 35illustrates an example in which a signal output from the circuit 1201 isinput to the other of the source and the drain of the transistor 1209.The logic value of a signal output from the second terminal of theswitch 1203 (the other of the source and the drain of the transistor1213) is inverted by the logic element 1206, and the inverted signal isinput to the circuit 1201 through the circuit 1220.

In the example of FIG. 35, a signal output from the second terminal ofthe switch 1203 (the other of the source and the drain of the transistor1213) is input to the circuit 1201 through the logic element 1206 andthe circuit 1220; however, one embodiment of the present invention isnot limited thereto. The signal output from the second terminal of theswitch 1203 (the other of the source and the drain of the transistor1213) may be input to the circuit 1201 without its logic value beinginverted. For example, in the case where the circuit 1201 includes anode in which a signal obtained by inversion of the logic value of asignal input from the input terminal is retained, the signal output fromthe second terminal of the switch 1203 (the other of the source and thedrain of the transistor 1213) can be input to the node.

In FIG. 35, the transistors included in the memory element 1200 exceptfor the transistor 1209 can each be a transistor in which a channel isformed in a layer formed using a semiconductor other than an oxidesemiconductor or in the substrate 1190. For example, the transistor canbe a transistor whose channel is formed in a silicon layer or a siliconsubstrate. Alternatively, all the transistors in the memory element 1200may be a transistor in which a channel is formed in an oxidesemiconductor layer. Further alternatively, in the memory element 1200,a transistor in which a channel is formed in an oxide semiconductorlayer can be included besides the transistor 1209, and a transistor inwhich a channel is formed in a layer including a semiconductor otherthan an oxide semiconductor or the substrate 1190 can be used for thereset of the transistors.

As the circuit 1201 in FIG. 35, for example, a flip-flop circuit can beused. As the logic element 1206, for example, an inverter or a clockedinverter can be used.

In a period during which the memory element 1200 is not supplied withthe power supply voltage, the semiconductor device of one embodiment ofthe present invention can retain data stored in the circuit 1201 by thecapacitor 1208 which is provided in the circuit 1202.

The off-state current of a transistor in which a channel is formed in anoxide semiconductor layer is extremely low. For example, the off-statecurrent of a transistor in which a channel is formed in an oxidesemiconductor layer is significantly lower than that of a transistor inwhich a channel is formed in silicon having crystallinity. Thus, whenthe transistor is used as the transistor 1209, a signal held in thecapacitor 1208 is retained for a long time also in a period during whichthe power supply voltage is not supplied to the memory element 1200. Thememory element 1200 can accordingly retain the stored content (data)also in a period during which the supply of the power supply voltage isstopped.

Since the above-described memory element performs pre-charge operationwith the switch 1203 and the switch 1204, the time required for thecircuit 1201 to retain original data again after the supply of the powersupply voltage is restarted can be shortened.

In the circuit 1202, a signal retained by the capacitor 1208 is input tothe gate of the transistor 1210. Therefore, after supply of the powersupply voltage to the memory element 1200 is restarted, the signalretained by the capacitor 1208 can be converted into the onecorresponding to the state (the on state or the off state) of thetransistor 1210 to be read from the circuit 1202. Consequently, anoriginal signal can be accurately read even when a potentialcorresponding to the signal retained by the capacitor 1208 varies tosome degree.

By applying the above-described memory element 1200 to a memory devicesuch as a register or a cache memory included in a processor, data inthe memory device can be prevented from being lost owing to the stop ofthe supply of the power supply voltage. Furthermore, shortly after thesupply of the power supply voltage is restarted, the memory device canbe returned to the same state as that before the power supply isstopped. Therefore, the power supply can be stopped even for a shorttime in the processor or one or a plurality of logic circuits includedin the processor, resulting in lower power consumption.

Although the memory element 1200 is used in a CPU in this embodiment,the memory element 1200 can also be used in an LSI such as a digitalsignal processor (DSP), a custom LSI, or a programmable logic device(PLD), and a radio frequency (RF) tag.

This embodiment can be combined as appropriate with any of the otherembodiments and examples in this specification.

Embodiment 7

In this embodiment, configuration examples of a display device using atransistor of one embodiment of the present invention are described.

<Circuit Configuration Example of Display Device>

FIG. 36A is a top view of the display device of one embodiment of thepresent invention. FIG. 36B is a circuit diagram illustrating a pixelcircuit that can be used in the case where a liquid crystal element isused in a pixel in the display device of one embodiment of the presentinvention. FIG. 36C is a circuit diagram illustrating a pixel circuitthat can be used in the case where an organic EL element is used in apixel in the display device of one embodiment of the present invention.

The transistor in the pixel portion can be formed in accordance withEmbodiments 1 to 3. The transistor can be easily formed as an n-channeltransistor, and thus part of a driver circuit that can be formed usingan n-channel transistor can be formed over the same substrate as thetransistor of the pixel portion. With the use of any of the transistorsdescribed in the above embodiments for the pixel portion or the drivercircuit in this manner, a highly reliable display device can beprovided.

FIG. 36A illustrates an example of a top view of an active matrixdisplay device. A pixel portion 701, a first scan line driver circuit702, a second scan line driver circuit 703, and a signal line drivercircuit 704 are formed over a substrate 700 of the display device. Inthe pixel portion 701, a plurality of signal lines extended from thesignal line driver circuit 704 are arranged and a plurality of scanlines extended from the first scan line driver circuit 702 and thesecond scan line driver circuit 703 are arranged. Note that pixels whichinclude display elements are provided in a matrix in respective regionswhere the scan lines and the signal lines intersect with each other. Thesubstrate 700 of the display device is connected to a timing controlcircuit (also referred to as a controller or a controller IC) through aconnection portion such as a flexible printed circuit (FPC).

In FIG. 36A, the first scan line driver circuit 702, the second scanline driver circuit 703, and the signal line driver circuit 704 areformed over the substrate 700 where the pixel portion 701 is formed.Accordingly, the number of components which are provided outside, suchas a driver circuit, can be reduced, so that a reduction in cost can beachieved. Furthermore, if the driver circuit is provided outside thesubstrate 700, wirings would need to be extended and the number ofwiring connections would increase. When the driver circuit is providedover the substrate 700, the number of wiring connections can be reduced.Consequently, an improvement in reliability or yield can be achieved.One or more of the first scan line driver circuit 702, the second scanline driver circuit 703, and the signal line driver circuit 704 may bemounted on the substrate 700 or provided outside the substrate 700.

<Liquid Crystal Display Device>

FIG. 36B illustrates an example of a circuit configuration of the pixel.Here, a pixel circuit which is applicable to a pixel of a VA liquidcrystal display device is illustrated as an example.

This pixel circuit can be applied to a structure in which one pixelincludes a plurality of pixel electrode layers. The pixel electrodelayers are connected to different transistors, and the transistors canbe driven with different gate signals. Accordingly, signals applied toindividual pixel electrode layers in a multi-domain pixel can becontrolled independently.

A scan line 712 of a transistor 716 and a scan line 713 of a transistor717 are separated so that different gate signals can be suppliedthereto. In contrast, a data line 714 is shared by the transistors 716and 717. The transistor described in any of Embodiments 1 to 3 can beused as appropriate as each of the transistors 716 and 717. Thus, ahighly reliable liquid crystal display device can be provided.

A first pixel electrode layer is electrically connected to thetransistor 716 and a second pixel electrode is electrically connected tothe transistor 717. The first pixel electrode and the second pixelelectrode are separated. There is no particular limitation on the shapesof the first pixel electrode and the second pixel electrode. Forexample, the first pixel electrode may have a V-like shape.

Agate electrode of the transistor 716 is connected to the scan line 712,and a gate electrode of the transistor 717 is connected to the scan line713. When different gate signals are supplied to the scan line 712 andthe scan line 713, operation timings of the transistor 716 and thetransistor 717 can be varied. As a result, alignment of liquid crystalscan be controlled.

Further, a storage capacitor may be formed using a capacitor wiring 710,a gate insulating layer functioning as a dielectric, and a capacitorelectrode electrically connected to the first pixel electrode layer orthe second pixel electrode layer.

The multi-domain pixel includes a first liquid crystal element 718 and asecond liquid crystal element 719. The first liquid crystal element 718includes the first pixel electrode layer, a counter electrode layer, anda liquid crystal layer therebetween. The second liquid crystal element719 includes the second pixel electrode layer, a counter electrodelayer, and a liquid crystal layer therebetween.

Note that a pixel circuit of the present invention is not limited tothat shown in FIG. 36B. For example, a switch, a resistor, a capacitor,a transistor, a sensor, a logic circuit, or the like may be added to thepixel circuit illustrated in FIG. 36B.

<Organic EL Display Device>

FIG. 36C illustrates another example of a circuit configuration of thepixel. Here, a pixel structure of a display device using an organic ELelement is shown.

In an organic EL element, by application of voltage to a light-emittingelement, electrons are injected from one of a pair of electrodes andholes are injected from the other of the pair of electrodes, into alayer containing a light-emitting organic compound; thus, current flows.The electrons and holes are recombined, and thus, the light-emittingorganic compound is excited. The light-emitting organic compound returnsto a ground state from the excited state, thereby emitting light. Owingto such a mechanism, this light-emitting element is referred to as acurrent-excitation light-emitting element.

FIG. 36C illustrates an applicable example of a pixel circuit. Here, onepixel includes two n-channel transistors. Furthermore, digital timegrayscale driving can be employed for the pixel circuit.

The configuration of the applicable pixel circuit and operation of apixel employing digital time grayscale driving are described.

A pixel 720 includes a switching transistor 721, a driver transistor722, a light-emitting element 724, and a capacitor 723. A gate electrodelayer of the switching transistor 721 is connected to a scan line 726, afirst electrode (one of a source electrode layer and a drain electrodelayer) of the switching transistor 721 is connected to a signal line725, and a second electrode (the other of the source electrode layer andthe drain electrode layer) of the switching transistor 721 is connectedto a gate electrode layer of the driver transistor 722. The gateelectrode layer of the driver transistor 722 is connected to a powersupply line 727 through the capacitor 723, a first electrode of thedriver transistor 722 is connected to the power supply line 727, and asecond electrode of the driver transistor 722 is connected to a firstelectrode (a pixel electrode) of the light-emitting element 724. Asecond electrode of the light-emitting element 724 corresponds to acommon electrode 728. The common electrode 728 is electrically connectedto a common potential line formed over the same substrate as the commonelectrode 728.

As the switching transistor 721 and the driver transistor 722, thetransistor described in any of Embodiments 1 to 3 can be used asappropriate. In this manner, a highly reliable organic EL display devicecan be provided.

The potential of the second electrode (the common electrode 728) of thelight-emitting element 724 is set to be a low power supply potential.Note that the low power supply potential is lower than a high powersupply potential supplied to the power supply line 727. For example, thelow power supply potential can be GND, 0V, or the like. The high powersupply potential and the low power supply potential are set to be higherthan or equal to the forward threshold voltage of the light-emittingelement 724, and the difference between the potentials is applied to thelight-emitting element 724, whereby current is supplied to thelight-emitting element 724, leading to light emission. The forwardvoltage of the light-emitting element 724 refers to a voltage at which adesired luminance is obtained, and includes at least a forward thresholdvoltage.

Note that gate capacitance of the driver transistor 722 may be used as asubstitute for the capacitor 723, so that the capacitor 723 can beomitted.

Next, a signal input to the driver transistor 722 is described. In thecase of a voltage-input voltage driving method, a video signal forsufficiently turning on or off the driver transistor 722 is input to thedriver transistor 722. In order for the driver transistor 722 to operatein a linear region, voltage higher than the voltage of the power supplyline 727 is applied to the gate electrode layer of the driver transistor722. Note that voltage higher than or equal to voltage which is the sumof power supply line voltage and the threshold voltage Vth of the drivertransistor 722 is applied to the signal line 725.

In the case of performing analog grayscale driving, a voltage greaterthan or equal to a voltage which is the sum of the forward voltage ofthe light-emitting element 724 and the threshold voltage V_(th) of thedriver transistor 722 is applied to the gate electrode layer of thedriver transistor 722. A video signal by which the driver transistor 722is operated in a saturation region is input, so that current is suppliedto the light-emitting element 724. In order for the driver transistor722 to operate in a saturation region, the potential of the power supplyline 727 is set higher than the gate potential of the driver transistor722. When an analog video signal is used, it is possible to supplycurrent to the light-emitting element 724 in accordance with the videosignal and perform analog grayscale driving.

Note that the configuration of the pixel circuit of the presentinvention is not limited to that shown in FIG. 36C. For example, aswitch, a resistor, a capacitor, a sensor, a transistor, a logiccircuit, or the like may be added to the pixel circuit illustrated inFIG. 36C.

In the case where the transistor shown in any of the above embodimentsis used for the circuit shown in FIGS. 36A to 36C, the source electrode(the first electrode) is electrically connected to the low potentialside and the drain electrode (the second electrode) is electricallyconnected to the high potential side. Furthermore, the potential of thefirst gate electrode may be controlled by a control circuit or the likeand the potential described above as an example, e.g., a potential lowerthan the potential applied to the source electrode, may be input to thesecond gate electrode through a wiring that is not illustrated.

For example, in this specification and the like, a display element, adisplay device which is a device including a display element, alight-emitting element, and a light-emitting device which is a deviceincluding a light-emitting element can employ a variety of modes or caninclude a variety of elements. A display element, a display device, alight-emitting element, or a light-emitting device include at least oneof the following, for example: an EL (electroluminescent) element (e.g.,an EL element including organic and inorganic materials, an organic ELelement, or an inorganic EL element), an LED (e.g., a white LED, a redLED, a green LED, or a blue LED), a transistor (a transistor which emitslight depending on current), an electron emitter, a liquid crystalelement, electronic ink, an electrophoretic element, a grating lightvalve (GLV), a plasma display panel (PDP), micro electro mechanicalsystems (MEMS), a digital micromirror device (DMD), a digital microshutter (DMS), MIRASOL (registered trademark), an interferometricmodulator display (IMOD) element, an electrowetting element, apiezoelectric ceramic display, and a display element using a carbonnanotube. Other than the above, display media whose contrast, luminance,reflectivity, transmittance, or the like is changed by electric orelectromagnetic action may be included. Note that examples of displaydevices having EL elements include an EL display. Examples of displaydevices including electron emitters are a field emission display (FED)and an SED-type flat panel display (SED: surface-conductionelectron-emitter display). Examples of display devices including liquidcrystal elements include a liquid crystal display (e.g., a transmissiveliquid crystal display, a transflective liquid crystal display, areflective liquid crystal display, a direct-view liquid crystal display,or a projection liquid crystal display). Examples of display devicesincluding electronic ink or electrophoretic elements include electronicpaper.

This embodiment can be combined as appropriate with any of the otherembodiments and examples in this specification.

Embodiment 8

In this embodiment, a display module using a semiconductor device of oneembodiment of the present invention is described with reference to FIG.37.

<Display Module>

In a display module 6000 in FIG. 37, a touch panel 6004 connected to anFPC 6003, a display panel 6006 connected to an FPC 6005, a backlightunit 6007, a frame 6009, a printed board 6010, and a battery 6011 areprovided between an upper cover 6001 and a lower cover 6002. Note thatthe backlight unit 6007, the battery 6011, the touch panel 6004, and thelike are not provided in some cases.

The semiconductor device of one embodiment of the present invention canbe used for, for example, the display panel 6006 and an integratedcircuit mounted on a printed circuit board.

The shapes and sizes of the upper cover 6001 and the lower cover 6002can be changed as appropriate in accordance with the sizes of the touchpanel 6004 and the display panel 6006.

The touch panel 6004 can be a resistive touch panel or a capacitivetouch panel and may be formed to overlap with the display panel 6006. Acounter substrate (sealing substrate) of the display panel 6006 can havea touch panel function. A photosensor may be provided in each pixel ofthe display panel 6006 so that an optical touch panel function is added.An electrode for a touch sensor may be provided in each pixel of thedisplay panel 6006 so that a capacitive touch panel function is added.

The backlight unit 6007 includes a light source 6008. The light source6008 may be provided at an end portion of the backlight unit 6007 and alight diffusing plate may be used.

The frame 6009 protects the display panel 6006 and also functions as anelectromagnetic shield for blocking electromagnetic waves generated fromthe printed board 6010. The frame 6009 may function as a radiator plate.

The printed board 6010 has a power supply circuit and a signalprocessing circuit for outputting a video signal and a clock signal. Asa power source for supplying power to the power supply circuit, anexternal commercial power source or the battery 6011 provided separatelymay be used. Note that the battery 6011 is not necessary in the casewhere a commercial power source is used.

The display module 6000 can be additionally provided with a member suchas a polarizing plate, a retardation plate, or a prism sheet.

This embodiment can be combined as appropriate with any of the otherembodiments and examples in this specification.

Embodiment 9

In this embodiment, application examples of the semiconductor device inone embodiment of the present invention will be described.

<Package Using a Lead Frame Interposer>

FIG. 38A is a perspective view illustrating a cross-sectional structureof a package using a lead frame interposer. In the package illustratedin FIG. 38A, a chip 751 corresponding to the semiconductor device of oneembodiment of the present invention is connected to a terminal 752 overan interposer 750 by wire bonding. The terminal 752 is placed on asurface of the interposer 750 on which the chip 751 is mounted. The chip751 may be sealed by a mold resin 753, in which case the chip 751 issealed such that part of each of the terminals 752 is exposed.

FIG. 38B illustrates the structure of a module of an electronic device(mobile phone) in which a package is mounted on a circuit board. In themodule of the mobile phone in FIG. 38B, a package 1802 and a battery1804 are mounted on a printed wiring board 1801. The printed wiringboard 1801 is mounted on a panel 1800 including a display element by anFPC 1803.

This embodiment can be combined as appropriate with any of the otherembodiments and examples in this specification.

Embodiment 10

In this embodiment, electronic devices and lighting devices of oneembodiment of the present invention will be described with reference todrawings.

<Electronic Device>

Electronic devices and lighting devices can be fabricated using thesemiconductor device of one embodiment of the present invention. Inaddition, highly reliable electronic devices and lighting devices can befabricated using the semiconductor device of one embodiment of thepresent invention. Furthermore, electronic devices and lighting devicesincluding touch sensors with improved detection sensitivity can befabricated using the semiconductor device of one embodiment of thepresent invention.

Examples of electronic devices are television devices (also referred toas TV or television receivers), monitors for computers and the like,cameras such as digital cameras and digital video cameras, digital photoframes, cellular phones (also referred to as portable telephonedevices), portable game machines, portable information terminals, audioplayback devices, large game machines such as pin-ball machines, and thelike.

In the case of having flexibility, the light-emitting device or lightingdevice of one embodiment of the present invention can be incorporatedalong a curved inside/outside wall surface of a house or a building or acurved interior/exterior surface of a car.

Furthermore, the electronic device of one embodiment of the presentinvention may include a secondary battery. It is preferable that thesecondary battery be capable of being charged by non-contact powertransmission.

Examples of the secondary battery include a lithium ion secondarybattery such as a lithium polymer battery using a gel electrolyte(lithium ion polymer battery), a lithium-ion battery, a nickel-hydridebattery, a nickel-cadmium battery, an organic radical battery, alead-acid battery, an air secondary battery, a nickel-zinc battery, anda silver-zinc battery.

The electronic device of one embodiment of the present invention mayinclude an antenna. When a signal is received by the antenna, theelectronic device can display an image, data, or the like on a displayportion. When the electronic device includes a secondary battery, theantenna may be used for non-contact power transmission.

FIG. 39A illustrates a portable game machine including a housing 7101, ahousing 7102, a display portion 7103, a display portion 7104, amicrophone 7105, speakers 7106, an operation key 7107, a stylus 7108,and the like. The semiconductor device of one embodiment of the presentinvention can be used for an integrated circuit, a CPU, or the likeincorporated in the housing 7101. When the light-emitting device of oneembodiment of the present invention is used as the display portion 7103or 7104, it is possible to provide a user-friendly portable game machinewith quality that hardly deteriorates. Although the portable gamemachine illustrated in FIG. 39A includes two display portions, thedisplay portion 7103 and the display portion 7104, the number of displayportions included in the portable game machine is not limited to two.

FIG. 39B illustrates a smart watch, which includes a housing 7302, adisplay portion 7304, operation buttons 7311 and 7312, a connectionterminal 7313, a band 7321, a clasp 7322, and the like. Thesemiconductor device of one embodiment of the present invention can beused for a memory, a CPU, or the like incorporated in the housing 7302.

FIG. 39C illustrates a portable information terminal, which includes adisplay portion 7502 incorporated in a housing 7501, operation buttons7503, an external connection port 7504, a speaker 7505, a microphone7506, and the like. The semiconductor device of one embodiment of thepresent invention can be used for a mobile memory, a CPU, or the likeincorporated in the housing 7501. Note that the display portion 7502 issmall- or medium-sized but can perform full high vision, 4k, or 8kdisplay because it has greatly high definition; therefore, asignificantly clear image can be obtained.

FIG. 39D illustrates a video camera including a first housing 7701, asecond housing 7702, a display portion 7703, operation keys 7704, a lens7705, a joint 7706, and the like. The operation keys 7704 and the lens7705 are provided for the first housing 7701, and the display portion7703 is provided for the second housing 7702. The first housing 7701 andthe second housing 7702 are connected to each other with the joint 7706,and the angle between the first housing 7701 and the second housing 7702can be changed with the joint 7706. Images displayed on the displayportion 7703 may be switched in accordance with the angle at the joint7706 between the first housing 7701 and the second housing 7702. Theimaging device of one embodiment of the present invention can be used ina portion corresponding to a focus of the lens 7705. The semiconductordevice of one embodiment of the present invention can be used for anintegrated circuit, a CPU, or the like incorporated in the first housing7701.

FIG. 39E illustrates a digital signage including a display portion 7902provided on a utility pole 7901. The semiconductor device of oneembodiment of the present invention can be used for a control circuit ofthe display portion 7902.

FIG. 40A illustrates a notebook personal computer, which includes ahousing 8121, a display portion 8122, a keyboard 8123, a pointing device8124, and the like. The semiconductor device of one embodiment of thepresent invention can be used for a CPU, a memory, or the likeincorporated in the housing 8121. Note that the display portion 8122 issmall- or medium-sized but can perform 8k display because it has greatlyhigh definition; therefore, a significantly clear image can be obtained.

FIG. 40B is an external view of an automobile 9700. FIG. 40C illustratesa driver's seat of the automobile 9700. The automobile 9700 includes acar body 9701, wheels 9702, a dashboard 9703, lights 9704, and the like.The semiconductor device of one embodiment of the present invention canbe used in a display portion and a control integrated circuit of theautomobile 9700. For example, the display device or input/output deviceof one embodiment of the present invention can be used in displayportions 9710 to 9715 illustrated in FIG. 40C.

The display portion 9710 and the display portion 9711 are displaydevices or input/output devices provided in an automobile windshield.The display device or input/output device of one embodiment of thepresent invention can be a see-through display device or input/outputdevice, through which the opposite side can be seen, by using alight-transmitting conductive material for its electrodes. Such asee-through display device or input/output device does not hinderdriver's vision during the driving of the automobile 9700. Therefore,the display device or input/output device of one embodiment of thepresent invention can be provided in the windshield of the automobile9700. Note that in the case where a transistor or the like for drivingthe display device or input/output device is provided in the displaydevice or input/output device, a transistor having light-transmittingproperties, such as an organic transistor using an organic semiconductormaterial or a transistor using an oxide semiconductor, is preferablyused.

The display portion 9712 is a display device provided on a pillarportion. For example, the display portion 9712 can compensate for theview hindered by the pillar portion by showing an image taken by animaging unit provided on the car body. The display portion 9713 is adisplay device provided on a dashboard portion. For example, the displayportion 9713 can compensate for the view hindered by the dashboardportion by showing an image taken by an imaging unit provided on the carbody. That is, showing an image taken by an imaging unit provided on theoutside of the car body leads to elimination of blind areas andenhancement of safety. In addition, showing an image so as to compensatefor the area which a driver cannot see makes it possible for the driverto confirm safety easily and comfortably.

FIG. 40D illustrates the inside of a car in which a bench seat is usedas a driver seat and a front passenger seat. A display portion 9721 is adisplay device or an input/output device provided in a door portion. Forexample, the display portion 9721 can compensate for the view hinderedby the door portion by showing an image taken by an imaging unitprovided on the car body. A display portion 9722 is a display deviceprovided in a steering wheel. A display portion 9723 is a display deviceprovided in the middle of a seating face of the bench seat. Note thatthe display device can be used as a seat heater by providing the displaydevice on the seating face or backrest and by using heat generated bythe display device as a heat source.

The display portion 9714, the display portion 9715, and the displayportion 9722 can display a variety of kinds of information such asnavigation data, a speedometer, a tachometer, a mileage, a fuel meter, agearshift indicator, and air-condition setting. The content, layout, orthe like of the display on the display portions can be changed freely bya user as appropriate. The information listed above can also bedisplayed on the display portions 9710 to 9713, 9721, and 9723. Thedisplay portions 9710 to 9715 and 9721 to 9723 can also be used aslighting devices. The display portions 9710 to 9715 and 9721 to 9723 canalso be used as heating devices.

FIG. 41A illustrates an external view of a camera 8000. The camera 8000includes a housing 8001, a display portion 8002, an operation button8003, a shutter button 8004, a connection portion 8005, and the like. Alens 8006 can be put on the camera 8000.

The connection portion 8005 includes an electrode to connect a finder8100, which is described below, a stroboscope, or the like.

Although the lens 8006 of the camera 8000 here is detachable from thehousing 8001 for replacement, the lens 8006 may be included in thehousing 8001.

Images can be taken at the press of the shutter button 8004. Inaddition, images can be taken at the touch of the display portion 8002which serves as a touch panel.

The display device or input/output device of one embodiment of thepresent invention can be used in the display portion 8002.

FIG. 41B shows the camera 8000 with the finder 8100 connected.

The finder 8100 includes a housing 8101, a display portion 8102, abutton 8103, and the like.

The housing 8101 includes a connection portion for engagement with theconnection portion 8005 of the camera 8000 so that the finder 8100 canbe connected to the camera 8000. The connection portion includes anelectrode, and an image or the like received from the camera 8000through the electrode can be displayed on the display portion 8102.

The button 8103 has a function of a power button, and the displayportion 8102 can be turned on and off with the button 8103.

The semiconductor device of one embodiment of the present invention canbe used for an integrated circuit and an image sensor included in thehousing 8101.

Although the camera 8000 and the finder 8100 are separate and detachableelectronic devices in FIGS. 41A and 41B, the housing 8001 of the camera8000 may include a finder having the display device or input/outputdevice of one embodiment of the present invention.

FIG. 41C illustrates an external view of a head-mounted display 8200.

The head-mounted display 8200 includes a mounting portion 8201, a lens8202, a main body 8203, a display portion 8204, a cable 8205, and thelike. The mounting portion 8201 includes a battery 8206.

Power is supplied from the battery 8206 to the main body 8203 throughthe cable 8205. The main body 8203 includes a wireless receiver or thelike to receive video data, such as image data, and display it on thedisplay portion 8204. The movement of the eyeball and the eyelid of auser is captured by a camera in the main body 8203 and then coordinatesof the points the user looks at are calculated using the captured datato utilize the eye of the user as an input means.

The mounting portion 8201 may include a plurality of electrodes so as tobe in contact with the user. The main body 8203 may be configured tosense current flowing through the electrodes with the movement of theuser's eyeball to recognize the direction of his or her eyes. The mainbody 8203 may be configured to sense current flowing through theelectrodes to monitor the user's pulse. The mounting portion 8201 mayinclude sensors, such as a temperature sensor, a pressure sensor, or anacceleration sensor so that the user's biological information can bedisplayed on the display portion 8204. The main body 8203 may beconfigured to sense the movement of the user's head or the like to movean image displayed on the display portion 8204 in synchronization withthe movement of the user's head or the like.

The semiconductor device of one embodiment of the present invention canbe used for an integrated circuit included in the main body 8203.

At least part of this embodiment can be implemented in combination withany of the embodiments described in this specification as appropriate.

Embodiment 11

In this embodiment, application examples of an RF tag using thesemiconductor device of one embodiment of the present invention will bedescribed with reference to FIGS. 42A to 42F.

<Application Examples of RF Tag>

The RF tag is widely used and can be provided for, for example, productssuch as bills, coins, securities, bearer bonds, documents (e.g.,driver's licenses or resident's cards, see FIG. 42A), vehicles (e.g.,bicycles, see FIG. 42B), packaging containers (e.g., wrapping paper orbottles, see FIG. 42C), recording media (e.g., DVD or video tapes, seeFIG. 42D), personal belongings (e.g., bags or glasses), foods, plants,animals, human bodies, clothing, household goods, medical supplies suchas medicine and chemicals, and electronic devices (e.g., liquid crystaldisplay devices, EL display devices, television sets, or cellularphones), or tags on products (see FIGS. 42E and 42F).

An RF tag 4000 of one embodiment of the present invention is fixed to aproduct by being attached to a surface thereof or embedded therein. Forexample, the RF tag 4000 is fixed to each product by being embedded inpaper of a book, or embedded in an organic resin of a package. Since theRF tag 4000 of one embodiment of the present invention can be reduced insize, thickness, and weight, it can be fixed to a product withoutspoiling the design of the product. Furthermore, bills, coins,securities, bearer bonds, documents, or the like can have anidentification function by being provided with the RF tag 4000 of oneembodiment of the present invention, and the identification function canbe utilized to prevent counterfeiting. Moreover, the efficiency of asystem such as an inspection system can be improved by providing the RFtag of one embodiment of the present invention for packaging containers,recording media, personal belongings, foods, clothing, household goods,electronic devices, or the like. Vehicles can also have higher securityagainst theft or the like by being provided with the RF tag of oneembodiment of the present invention.

As described above, by using the RF tag including the semiconductordevice of one embodiment of the present invention for each applicationdescribed in this embodiment, power for operation such as writing orreading of data can be reduced, which results in an increase in themaximum communication distance. Moreover, data can be held for anextremely long period even in the state where power is not supplied;thus, the RF tag can be preferably used for application in which data isnot frequently written or read.

This embodiment can be combined as appropriate with any of the otherembodiments and examples in this specification.

EXAMPLE 1

The transistor described in Embodiment 1 was fabricated and describedhere are observations of a cross section of the transistor.

Samples were fabricated by the method described in Embodiment 1.

As the insulating layer 110, a 100-nm-thick silicon oxynitride film wasformed by a plasma CVD method. The silicon oxynitride film was formedunder the following conditions: the deposition gas flow rates of silaneand dinitrogen monoxide were 5 sccm and 1000 sccm, respectively; thepressure in a chamber was controlled to be 133.30 Pa using adiaphragm-type baratron sensor and an APC valve; the RF power frequencywas 13.56 MHz; the power was 35 W; the distance between electrodes was20 mm; and the substrate heating temperature was 325° C.

The oxide insulating layer 121 was formed to a thickness of 20 nm by asputtering method using a target of In:Ga:Zn=1:3:4 (atomic ratio). Theoxide insulating layer 121 was formed under the following conditions:the pressure in a chamber was 0.7 Pa; a DC power source was used and thepower was 0.5 kW; the sputtering gas flow rates of an Ar gas and anoxygen gas were 40 sccm and 5 sccm, respectively; the distance betweenthe sample and the target was 60 mm; and the substrate heatingtemperature was 200° C.

The oxide semiconductor layer 122 was formed to a thickness of 15 nm bya sputtering method using a target of In:Ga:Zn=1:1:1. The oxidesemiconductor layer 122 was formed under the following conditions: thepressure in a chamber was 0.7 Pa; a DC power source was used and thepower was 0.5 kW; the sputtering gas flow rates of an Ar gas and anoxygen gas were 30 sccm and 15 sccm, respectively; the distance betweenthe sample and the target was 60 mm; and the substrate heatingtemperature was 300° C.

As the source electrode layer 130 and the drain electrode layer 140, a20-nm-thick tungsten film was formed by a sputtering method. Thetungsten film was formed under the following conditions: the pressure ina chamber was 0.8 Pa; a DC power source was used and the power was 1 kW;the sputtering gas flow rates of an Ar gas and a heated Ar gas were 80sccm and 10 sccm, respectively; the distance between the substrate andthe target was 60 mm; and the substrate heating temperature was 130° C.

An organic resin and a resist were applied onto the tungsten film, and aresist mask was formed by patterning using an electron beam (EB)lithography system. The organic resin and the tungsten film wereprocessed by an ICP dry etching method using the resist mask. Theprocessing was performed for 16 seconds under the following conditions:the etching gas flow rates of chlorine and tetrafluoromethane were 60sccm and 40 sccm, respectively; the ICP power was 2000 W; Bias power was50 W; the substrate temperature was −10° C.; and the pressure was 0.67Pa.

Then, a first oxide insulating film and an oxide semiconductor film wereprocessed to be the oxide insulating layer 121 and the oxidesemiconductor layer 122, respectively, by a dry etching method usingend-point detection under the following conditions: the etching gas flowrates of methane and argon were 16 sccm and 32 sccm, respectively; andthe substrate heating temperature was 70° C.

As the insulating layer 175, a silicon oxynitride film was formed by aplasma CVD method. The silicon oxynitride film was formed to a thicknessof 350 nm under the following conditions: the deposition gas flow ratesof silane and dinitrogen monoxide were 5 sccm and 1000 sccm,respectively; the pressure in a chamber was controlled to be 133.30 Pausing a diaphragm-type baratron sensor and an APC valve; the RF powerfrequency was 13.56 MHz; the power was 35 W; the distance betweenelectrodes was 20 mm; and the substrate heating temperature was 325° C.

After the deposition of the silicon oxynitride film, planarizationtreatment was performed by a CMP method.

After the planarization treatment, an organic resin film and aphotosensitive resist were applied onto the silicon oxynitride film, anda resist mask was formed by patterning using an EB lithography system.The silicon oxynitride film and the organic resin film were processed toform the groove portion 174 by an ICP dry etching method using theresist mask.

The processing by an ICP dry etching method included two steps. Thefirst step was performed for 15 seconds under the following conditions:the distance between the upper electrode and the substrate was 40 mm;the pressure was 6.5 Pa; the power of the RF power source was 1000 W onthe upper side and 100 W on the lower side; the etching gas flow rate oftetrafluoromethane was 40 sccm; and the chamber temperatures were 60°C., 50° C., and 20° C. in the upper portion, the side wall portion, andthe lower portion, respectively.

The second step was performed for 38 seconds under the followingconditions: the distance between the upper electrode and the substratewas 25 mm; the pressure was 3.3 Pa; the power of the RF power source was500 W on the upper side and 1150 W on the lower side; the etching gasflow rates of argon, oxygen, and hexafluoro-1,3-butadiene were 800 sccm,30 sccm, and 22 sccm, respectively; and the chamber temperatures were60° C., 50° C., and 20° C. in the upper portion, the side wall portion,and the lower portion, respectively.

Then, the tungsten film exposed by the above steps was processed by anICP dry etching method. The etching was performed for 20 seconds underthe following conditions: the pressure was 2.0 Pa; the power of the RFpower source was 1000 W on the upper side and 25 W on the lower side;the etching gas flow rates of chlorine and tetrafluoromethane were each40 sccm; and the substrate temperature was −10° C.

As the gate insulating layer 150, a silicon oxide film was formed by aplasma CVD method. The silicon oxide film was formed to a thickness of10 nm under the following conditions: the deposition gas flow rates ofsilane and dinitrogen monoxide were 1 sccm and 800 sccm, respectively;the pressure in a chamber was controlled to be 200 Pa using adiaphragm-type baratron sensor and an APC valve; the RF power frequencywas 60 MHz; the power was 150 W; the distance between electrodes was 28mm; and the substrate heating temperature was 350° C.

As the gate electrode layer 161 and the gate electrode layer 162, a10-nm-thick titanium nitride film and a 150-nm-thick tungsten film thatwere formed by a metal CVD method were used, respectively. Note that thetitanium nitride film was formed by an ALD method.

The titanium nitride film was formed in the following manner: 50 sccm oftitanium tetrachloride was introduced for 0.05 seconds and adsorbed onthe gate insulating layer 150; 4500 sccm of a nitrogen gas wasintroduced for 0.2 seconds and purging was performed; 2700 sccm of anammonia gas was introduced for 0.3 seconds and adsorbed on the gateinsulating layer 150; and 4000 sccm of a nitrogen gas was introduced for0.3 seconds. These steps were regarded as one cycle, and the filmthickness was controlled by changing the number of cycles. Furthermore,the substrate stage temperature was 412° C., the pressure was 667 Pa,and the distance between the substrate stage and the gas injection stagewas 3 mm.

The tungsten film was formed in three steps.

In the first step, tungsten was deposited to a thickness of 3 nm inthree cycles under the following conditions: the deposition gas flowrates of tungsten hexafluoride, silane, argon, nitrogen, and argon forthe rear side of the stage were 160 sccm, 400 sccm, 6000 sccm, 2000sccm, and 4000 sccm, respectively; the pressure in a chamber was 1000Pa; and the substrate stage temperature was 390° C.

In the second step, tungsten was deposited to a thickness of 41 nm underthe following conditions: the deposition gas flow rates of tungstenhexafluoride, argon, nitrogen, and argon for the rear side of the stagewere 250 sccm, 2000 sccm, 200 sccm, and 4000 sccm, respectively; thedeposition gas flow rates of hydrogen were 2200 sccm and 1700 sccm (agas line was divided into two); the pressure in a chamber was 10666 Pa;and the substrate stage temperature was 390° C.

In the third step, tungsten was deposited to a thickness of 106 nm underthe following conditions: the deposition gas flow rates of tungstenhexafluoride, argon, nitrogen, and argon for the rear side of the stagewere 250 sccm, 2000 sccm, 200 sccm, and 4000 sccm, respectively; thedeposition gas flow rates of hydrogen were 2200 sccm and 1700 sccm (agas line was divided into two); the pressure in a chamber was 10666 Pa;and the substrate stage temperature was 390° C.

After the titanium nitride film and the tungsten film were formed,planarization treatment was performed by a CMP method until theinsulating layer 175 was exposed.

The transistor was observed by STEM using HD-2300 produced by HitachiHigh-Technologies Corporation. FIG. 43 shows the observations of thecross section of the transistor by STEM.

As shown in FIG. 43, the transistor includes the insulating layer 110,the oxide insulating layer 121, the oxide semiconductor layer 122, thesource electrode layer 130, the drain electrode layer 140, the gateinsulating layer 150, the gate electrode layer 160, and the insulatinglayer 175. The insulating layer 175 has an opening portion and theopening portion is filled with the gate insulating layer 150 and thegate electrode layer 160.

In addition, the insulating layer 175 has a tapered shape and a roundshape; thus, the embeddability of the gate insulating layer 150 and thegate electrode layer 160 can be improved.

With such a structure, the gate electrode layer 160, the sourceelectrode layer 130, and the drain electrode layer 140 can be formed ina self-aligned manner; thus, alignment accuracy can be improved andminiaturized transistors can be manufactured more easily. In addition,parasitic capacitance between the gate electrode layer 160 and thesource electrode layer 130 or between the gate electrode layer 160 andthe drain electrode layer 140 can be reduced, so that the transistorcharacteristics (e.g., frequency characteristics) can be improved.

EXAMPLE 2

In this example, results of observing cross sections of the transistorfabricated by the method described in Embodiment 1 will be described.For the processing similar to that in Example 1, the description inExample 1 is referred to.

As the insulating layer 175, a silicon oxynitride film was formed by aplasma CVD method. The silicon oxynitride film was formed to a thicknessof 320 nm under the following conditions: the deposition gas flow ratesof silane and dinitrogen monoxide were 5 sccm and 1000 sccm,respectively; the pressure in a chamber was controlled to be 133.30 Pausing a diaphragm-type baratron sensor and an APC valve; the RF powerfrequency was 13.56 MHz; the power was 35 W; the distance betweenelectrodes was 20 mm; and the substrate heating temperature was 325° C.

The insulating layer 175 was formed by an ICP dry etching method in twosteps. The first step was performed for 15 seconds under the followingconditions: the distance between the upper electrode and the substratewas 40 mm; the pressure was 6.5 Pa; the power of the RF power source was1000 W on the upper side and 100 W on the lower side; the etching gasflow rate of tetrafluoromethane was 100 sccm; and the chambertemperatures were 60° C., 50° C., and 20° C. in the upper portion, theside wall portion, and the lower portion, respectively.

The second step was performed for 42 seconds under the followingconditions: the distance between the upper electrode and the substratewas 25 mm; the pressure was 3.3 Pa; the power of the RF power source was500 W on the upper side and 1150 W on the lower side; the etching gasflow rates of argon, oxygen, and hexafluoro-1,3-butadiene were 800 sccm,30 sccm, and 22 sccm, respectively; and the chamber temperatures were60° C., 50° C., and 20° C. in the upper portion, the side wall portion,and the lower portion, respectively.

Then, the tungsten film exposed by the above steps was processed by anICP dry etching method. The etching was performed for 10 seconds underthe following conditions: the pressure was 2.0 Pa; the power of the RFpower source was 1000 W on the upper side and 25 W on the lower side;the etching gas flow rates of chlorine, tetrafluoromethane, and oxygenwere 14 sccm, 28 sccm, and 28 sccm, respectively; and the substratetemperature was −10° C.

The oxide insulating layer 123 was formed to a thickness of 5 nm by asputtering method using a target of In:Ga:Zn=1:3:2 (atomic ratio). Theoxide insulating layer 123 was formed under the following conditions:the pressure in a chamber was 0.7 Pa; a DC power source was used and thepower was 0.5 kW; the sputtering gas flow rates of an Ar gas and anoxygen gas were 30 sccm and 15 sccm, respectively; the distance betweenthe sample and the target was 60 mm; and the substrate heatingtemperature was 200° C.

The transistor was observed by STEM as in Example 1. FIGS. 44A and 44Bshow the results of observing the cross sections of the transistor bySTEM.

As shown in FIGS. 44A and 44B, the transistor fabricated in this exampleincludes the insulating layer 110, the oxide insulating layer 121, theoxide semiconductor layer 122, the oxide insulating layer 123, thesource electrode layer 130, the drain electrode layer 140, the gateinsulating layer 150, the gate electrode layer 160, and the insulatinglayer 175. In addition, in the transistor, the groove portion 174 isprovided and the insulating layer 175 has a tapered shape. The structureof the transistor is substantially the same as the structure shown inFIGS. 1A and 1B, and the present invention can improve the embeddabilityof the oxide insulating layer 123, the gate insulating layer 150, andthe gate electrode layer 160 in the groove portion 174.

EXAMPLE 3

In this example, measurement results of electrical characteristics oftransistors fabricated using one embodiment of the present invention areshown.

In this example, for the portions where processing conditions similar tothose in Examples 1 and 2 were used, the descriptions in Examples 1 and2 are referred to.

After the insulating layer 110 was formed, planarization treatment usinga CMP method and heat treatment were performed. The heat treatment wasperformed at 450° C. under a nitrogen atmosphere for one hour, and thenperformed at 450° C. under vacuum for one hour.

Furthermore, oxygen addition treatment was performed on the insulatinglayer 110 by an ion implantation method. Note that the oxygen additiontreatment was performed under the following conditions: the accelerationvoltage was 60 kV; and the dose of oxygen was 2.0×10¹⁶ ions/cm².

In addition, after the first oxide insulating film and the oxidesemiconductor film were formed, heat treatment was performed. The heattreatment was performed at 450° C. under a nitrogen atmosphere for onehour, and then at 450° C. under an oxygen atmosphere for one hour.

In some samples, the oxide semiconductor layer 122 was formed to athickness of 15 nm by a sputtering method using a target ofIn:Ga:Zn=4:2:4.1. The oxide semiconductor layer 122 was formed using aturbo molecular pump and a cryotrap under the following conditions: thepressure in a chamber was 0.7 Pa; a DC power source was used and thepower was 0.5 kW; the sputtering gas flow rates of an Ar gas and anoxygen gas were 30 sccm and 15 sccm, respectively; the distance betweenthe sample and the target was 60 mm; and the substrate heatingtemperature was 200° C.

Before the insulating layer 170 was formed, a silicon oxynitride filmwas formed by a plasma CVD method. The silicon oxynitride film wasformed to a thickness of 50 nm under the following conditions: thedeposition gas flow rates of silane and dinitrogen monoxide were 5 sccmand 1000 sccm, respectively; the pressure in a chamber was controlled tobe 133.30 Pa using a diaphragm-type baratron sensor and an APC valve;the RF power frequency was 13.56 MHz; the power was 35 W; the distancebetween electrodes was 20 mm; and the substrate heating temperature was325° C.

Furthermore, in some samples, oxygen addition treatment was performed onthe silicon oxynitride film by an ion implantation method (Step 1). Theoxygen addition treatment was performed under the following conditions:the acceleration voltage was 5 kV; and the dose of oxygen was 1.0×10¹⁶ions/cm².

In addition, in some samples, heat treatment was performed after thesilicon oxynitride film was formed (Step 2). The heat treatment wasperformed at 350° C. under an oxygen atmosphere for one hour.

Furthermore, the insulating layer 170 was formed to a thickness of 40 nmby a sputtering method using an aluminum oxide target. The insulatinglayer 170 was formed under the following conditions: the pressure in achamber was 0.4 Pa; an RF power source was used and the power was 2.5kW; the sputtering gas flow rates of an Ar gas and an oxygen gas wereeach 25 sccm; the distance between the sample and the target was 60 mm;and the substrate heating temperature was 250° C.

In addition, heat treatment was performed after the insulating layer 170was formed. The heat treatment was performed at 350° C. under an oxygenatmosphere for one hour.

Then, an insulating layer and a wiring layer that are needed inmeasuring the electrical characteristics of the transistors were formed.

Table 1 shows step conditions which are different between samples (thecomposition of the oxide semiconductor layer 122, the oxygen additiontreatment (Step 1), and the heat treatment (Step 2)) in themanufacturing process of the above transistors.

TABLE 1 Oxide Step 1 Step 2 semiconductor (Oxygen addition (Heat layer122 treatment) treatment) Condition 1 In:Ga:Zn = 4:2:4.1 not performedperformed Condition 2 In:Ga:Zn = 1:1:1 not performed performed Condition3 In:Ga:Zn = 4:2:4.1 not performed not performed Condition 4 In:Ga:Zn =1:1:1 not performed not performed Condition 5 In:Ga:Zn = 1:1:1 performedperformed Condition 6 In:Ga:Zn = 1:1:1 performed not performed

FIG. 45 shows the Ids-Vgs measurement results of the fabricatedtransistors. The channel length of the transistors was 34 nm, and thechannel width thereof was 38 nm. The drain voltages (Vd) were 0.1 V and1.0 V.

As shown in FIG. 45, in all the conditions, high on-state current andoff-state current lower than or equal to the lower measurement limitwere obtained. Under Condition 4, variations in characteristics aresmall; thus, it is found that the present invention can providetransistors with small variations in characteristics.

In addition, FIG. 46 shows the Ids-Vgs measurement results of one pointin the substrate surface under Condition 4.

As shown in FIG. 46, when Vds is 0.1 V and 1.0 V, the gate voltage(V_(shift)) at a drain current of 1×10⁻¹² A is larger than 0 V, whichmeans that normally-off characteristics are obtained, and the drainvoltage dependence of V_(shift) tends to be small. In addition, when Vdsis 1.0 V, high on-state current characteristics are obtained.

Next, the Ids-Vgs measurement and the reliability evaluation wereperformed on transistors each having a channel length of 58 nm and achannel width of 62 nm.

The Ids-Vgs measurement was performed at Vd of 0.1 V and 1.2 V. Thereliability evaluation was performed in the following manner: thepositive gate BT test (+GBT test), the negative gate BT test (−GBTtest), or the drain BT test (+DBT test) was performed, and then theIds-Vgs measurement was performed at Vds of 0 V and 1.8 V. Thereliability test was performed on the transistors formed under Condition2, Condition 4, Condition 5, and Condition 6.

The +GBT test was performed at Vgs of +1.8 V at 150° C. for one hour,and variations in characteristics over time were measured. The −GBT testwas performed at Vgs of −1.8 V at 150° C. for one hour, and variationsin characteristics over time were measured. The +DBT test was performedat Vds of +1.8 V at 150° C. for one hour, and variations incharacteristics over time were measured.

FIG. 47 shows the Ids-Vgs measurement results of the transistors eachhaving a channel length of 58 nm and a channel width of 62 nm, and FIG.48 shows the results of the reliability tests.

In FIG. 47, favorable characteristics are obtained as in FIG. 45.Furthermore, as shown in FIG. 48, in all of the reliability tests,variations in characteristics are small; thus, it is found that thetransistors fabricated using the present invention can have highreliability.

Thus, combination of the above-described electrical characteristics withthe characteristics obtained in the other examples makes it possible tostably manufacture LSIs for low-power electronic devices, and the like,which cannot be achieved by using Si.

EXAMPLE 4

In this example, the measurement results of the frequencycharacteristics of the transistors fabricated using the presentinvention are described.

Here, the frequency characteristics of the transistors under Condition 3and Condition 4 shown in Example 3 were measured. Condition 3 isdifferent from Condition 4 in only the composition of the oxidesemiconductor layer 122. The oxide semiconductor layer 122 underCondition 3 was formed to a thickness of 15 nm by a sputtering methodusing a target of In:Ga:Zn=4:2:4.1, and the oxide semiconductor layer122 under Condition 4 was formed to a thickness of 15 nm by a sputteringmethod using a target of In:Ga:Zn=1:1:1.

The transistors were each designed with a channel length (L) of 30 nm or60 nm and a channel width (W) of 30 nm and evaluated.

A network analyzer used in the measurement has a standard impedance of50 Q. When the impedance of a transistor to be subjected to themeasurement is higher than the standard impedance, measurement accuracyis decreased. Thus, the impedance was decreased by connecting aplurality of transistors in parallel to increase the sum of channelwidths of the transistors. Specifically, 600 transistors each having theabove-described size were connected in parallel to measure frequencycharacteristics.

FIG. 49, FIG. 50, and FIG. 51 each show the layout of transistors thatwere subjected to the measurement.

FIG. 49 is a top view illustrating a transistor where 600 transistorseach having a channel width of 30 nm are connected in parallel andmeasurement terminals. A terminal A is electrically connected to a gateof the transistor. A terminal B is electrically connected to one of asource and a drain of the transistor. A terminal C is supplied with aGND potential and is electrically connected to the other of the sourceand the drain of the transistor. Transistors are arranged in Area 1.

FIG. 50 is an enlarged view of Area 1 in the top view of FIG. 49. Theterminal A is electrically connected to the gate of the transistor, andthe terminals B and C are electrically connected to the source and thedrain of the transistor.

FIG. 51 is an enlarged view of Area 2 in the top view of FIG. 50. Theterminal A is electrically connected to the gate of the transistor, andthe terminals B and C are electrically connected to the source and thedrain of the transistor.

A network analyzer was used in the measurement. A network analyzerN5247A produced by Agilent Technologies and SMUs 6242 and 6241A producedby ADC CORPORATION were used.

At the same time as the measurement of a target element (device undertest (DUT)), Open and Short test element groups (TEG) were measured, andthe characteristics of the DUT were obtained (this is also calledde-embedding).

Next, S parameters were measured by the network analyzer, and cutofffrequency (f_(T)) was calculated from the S parameters. The cutofffrequency (f_(T)) is defined as frequency at which a currentamplification factor or an extrapolated current amplification factorbecomes 1.

FIG. 52 shows measurement results of frequency characteristics. FIG. 52shows measurement results of transconductance (g_(m)), and the frequencywas measured based on the results at Vd of 2.0 V and Vg of 2.0 V. FIG.52 shows data after de-embedding based on the measured S parameters. InFIG. 52, the data after de-embedding is shown in a graph whose verticalaxis represents RF Gain [dB].

As shown in FIG. 52, cutoff frequency f_(T) calculated from anextrapolated value is 20.14 GHz when L is 30 nm under Condition 3, 7.86GHz when L is 30 nm under Condition 4, and 8.03 GHz when L is 60 nmunder Condition 4.

Therefore, it is found that the transistor using the present inventionhas high frequency characteristics and can achieve high-speed operationwhen the transistor is used in a memory circuit, a logic circuit, or ananalog circuit. Thus, combination of such characteristics with thecharacteristics obtained in the other examples makes it possible tostably manufacture LSIs and the like which can achieve low-powerconsumption and high-speed operation, which cannot be achieved by usingSi.

EXAMPLE 5

In this example, results of observing cross sections of the transistorfabricated by the method described in Embodiment 1 will be described.For the processing similar to that in Examples 1 and 2, the descriptionin Examples 1 and 2 is referred to.

In this example, before the insulating layer 175 was formed, a tungstenfilm and a silicon nitride film which are to be a hard mask were formedover the planarized silicon oxynitride film. The tungsten film wasformed to a thickness of 30 nm by a sputtering method, and the siliconnitride film was formed to a thickness of 50 nm by a plasma CVD method.

Then, a resist mask was formed by a lithography process, and then a hardmask was formed by an ICP dry etching method in four steps. The firststep was performed for 13 seconds under the following conditions: thedistance between the upper electrode and the substrate was 80 mm; thepressure was 3.0 Pa; the power of the RF power source was 500 W on theupper side and 100 W on the lower side; the etching gas flow rate oftetrafluoromethane was 80 sccm; and the chamber temperature in the lowerportion was 20° C.

The second step was performed for 28 seconds under the followingconditions: the distance between the upper electrode and the substratewas 80 mm; the pressure was 5.3 Pa; the power of the RF power source was550 W on the upper side and 350 W on the lower side; the etching gasflow rates of trifluoromethane and oxygen were 67 sccm and 13 sccm,respectively; and the chamber temperature in the lower portion was 20°C.

The third step was performed for 3 seconds under the followingconditions: the distance between the upper electrode and the substratewas 100 mm; the pressure was 1.3 Pa; the power of the RF power sourcewas 1000 W on each of the upper side and the lower side; the etching gasflow rates of tetrafluoromethane, oxygen, and chlorine were 22 sccm, 22sccm, and 11 sccm, respectively; and the chamber temperature in thelower portion was 20° C.

The fourth step was performed for 13 seconds under the followingconditions: the distance between the upper electrode and the substratewas 100 mm; the pressure was 0.6 Pa; the power of the RF power sourcewas 1000 W on the upper side and 100 W on the lower side; the etchinggas flow rates of tetrafluoromethane, oxygen, and chlorine were 22 sccm,22 sccm, and 11 sccm, respectively; and the chamber temperature in thelower portion was 20° C.

Then, the silicon oxynitride film exposed by the above steps wasprocessed by an ICP dry etching method. The etching was performed for 42seconds under the following conditions: the distance between the upperelectrode and the substrate was 25 mm; the pressure was 3.3 Pa; thepower of the RF power source was 500 W on the upper side and 1150 W onthe lower side; the etching gas flow rates of argon, oxygen, andhexafluoro-1,3-butadiene were 800 sccm, 30 sccm, and 22 sccm,respectively; and the chamber temperature in the lower portion was 20°C.

Then, the tungsten film exposed by the above steps was processed by anICP dry etching method in two steps.

The first step was performed for 3 seconds under the followingconditions: the distance between the upper electrode and the substratewas 100 mm; the pressure was 1.3 Pa; the power of the RF power sourcewas 1000 W on the upper side and 50 W on the lower side; the etching gasflow rates of tetrafluoromethane, oxygen, and chlorine were 22 sccm, 22sccm, and 11 sccm, respectively; and the chamber temperature in thelower portion was 20° C.

The second step was performed for 12 seconds under the followingconditions: the distance between the upper electrode and the substratewas 100 mm; the pressure was 0.6 Pa; the power of the RF power sourcewas 1000 W on the upper side and 50 W on the lower side; the etching gasflow rates of tetrafluoromethane, oxygen, and chlorine were 22 sccm, 22sccm, and 11 sccm, respectively; and the chamber temperature in thelower portion was 20° C.

The transistor was observed by STEM as in Example 1 and Example 2. FIGS.53A and 53B show the results of observing the cross sections of thetransistor by STEM.

As shown in FIGS. 53A and 53B, the transistor fabricated in this exampleincludes the insulating layer 110, the oxide insulating layer 121, theoxide semiconductor layer 122, the oxide insulating layer 123, thesource electrode layer 130, the drain electrode layer 140, the gateinsulating layer 150, the gate electrode layer 160, and the insulatinglayer 175. In addition, in the transistor, the groove portion 174 isprovided, the insulating layer 175 has a tapered shape, and the sidesurface of the insulating layer 175 is substantially vertical. Thiscross section is substantially the same as the cross section shown inFIG. 14B. With such a shape, variations in shape of the transistors canbe inhibited, so that the channel lengths can be stabilized andvariations in transistor characteristics can be reduced.

Therefore, with the present invention, transistors in which variationsin characteristics are inhibited and parasitic capacitance is reducedcan be manufactured.

EXAMPLE 6

In this example, a transistor was fabricated by the method described inEmbodiment 1 and the cross section of the transistor was observed. Theobservation results will be described with reference to FIG. 54. For theprocessing similar to that in Example 1, Example 2, and Example 5, thedescription in Example 1, Example 2, and Example 5 is referred to.

This example is different from Example 5 in a process size of the resistmask used in manufacture of the transistor.

The transistor was observed by STEM as in Example 1, Example 2, andExample 5. FIG. 54 shows the results of observing the cross section ofthe transistor by STEM.

As shown in FIG. 54, in the transistor fabricated in this example, thegroove portion 174 is provided and the side surface of the insulatinglayer 175 is substantially vertical as in Example 5. The channel lengthof the transistor is 30.5 nm; thus, it is found that a miniaturizedtransistor is fabricated. With such a shape, even in a miniaturizedtransistor, variations in shape of the transistors can be inhibited, sothat the channel lengths can be stabilized and variations in transistorcharacteristics can be reduced.

Therefore, with the present invention, transistors in which variationsin characteristics are inhibited and parasitic capacitance is reducedcan be manufactured.

EXAMPLE 7

In this example, measurement results of electrical characteristics oftransistors fabricated by the method described in Embodiment 1 will bedescribed with reference to FIG. 55, FIG. 56, and FIG. 57.

Fabrication conditions of transistors used in this example are similarto those in Example 3.

Measurement results of frequency will be described. The frequency wasmeasured using a transistor fabricated under Condition 3 in Example 3 atVd of 2.0 V and Vg of 2.0 V. The transistor has a channel length of 30nm and a channel width of 18 nm (600 transistors each having a channelwidth of 30 nm were connected in parallel).

FIG. 55 shows measurement results of frequency characteristics. FIG. 55shows measurement results of transconductance (g_(m)), and the frequencywas measured based on the results at Vd of 2.0 V and Vg of 2.0 V. FIG.55 shows data after de-embedding based on the measured S parameters. InFIG. 55, the data after de-embedding is shown in a graph whose verticalaxis represents RF Gain [dB].

As shown in FIG. 55, cutoff frequency f_(T) calculated from anextrapolated value is 28.3 GHz when L is 30 nm; that is, high frequencywas obtained.

Next, measurement results of off-leakage current will be described.

By the use of a transistor fabricated under Condition 2 in Example 3,the off-leakage current was measured at Vd of 1.8 V and a measurementtemperature of 150° C. in an air atmosphere. The transistor has achannel length of 30 nm or 60 nm and a channel width of 18 nm (300transistors each having a channel width of 60 nm were connected inparallel).

FIG. 56 shows the measurement results of off-leakage current.

As shown in FIG. 56, off-leakage current is lower than or equal to thelower measurement limit at 150° C. In consideration of the accelerationfactor depending on temperature, in the case where the channel width is60 nm, the off-leakage current of the transistor fabricated using thepresent invention is lower than or equal to 100 zA, which is extremelylow, at 85° C.

Next, measurement results of reliability will be described.

The reliability measurement was performed in the following manner: tothe transistor fabricated under Condition 6 in Example 3, stress wasapplied at Vd of 1.8 V and Vg of 0 V at 150° C. for one hour, and theId-Vg characteristics when Vd was 0.1 V or 1.8 V before and after thestress test were measured. The transistor has a channel length of 58 nmand a channel width of 62 nm. After the above measurement, the sourceelectrode and the drain electrode were switched, and the Id-Vgcharacteristics measurement was performed.

In addition, a transistor subjected to additional heat treatment (heattreatment at 400° C. in a nitrogen atmosphere for one hour) after beingfabricated was similarly evaluated.

FIG. 57 shows Id-Vg measurement results.

As shown in FIG. 57, additional heat treatment is performed after thetransistor was fabricated, whereby variations in characteristics beforeand after the source electrode and the drain electrode are switchedafter the stress test can be inhibited. This is probably because, by theheat treatment, defects in the film were repaired and the density ofinterface states was reduced.

Note that variations in characteristics can also be effectivelyinhibited by performing heat treatment not only after the transistor isfabricated but also after each insulating layer is formed.

Therefore, it is found that the transistor using the present inventionhas high frequency characteristics and can achieve high-speed operationwhen the transistor is used in a memory circuit, a logic circuit, or ananalog circuit. It is also found that the off-leakage current can beextremely low and variations in characteristics can be inhibited. Thus,combination of such characteristics with the characteristics obtained inthe other examples can make it possible to stably manufacture LSIs andthe like which can achieve low-power consumption and high-speedoperation, which cannot be achieved by using Si.

EXPLANATION OF REFERENCE

10: transistor, 11: transistor, 12: transistor, 13: transistor, 100:substrate, 110: insulating layer, 120: oxide semiconductor layer, 121:oxide insulating layer, 122: oxide semiconductor layer, 123: oxideinsulating layer, 123 a: oxide insulating film, 130: source electrodelayer, 130 b: conductive layer, 131: source electrode layer, 140: drainelectrode layer, 141: drain electrode layer, 150: gate insulating layer,150 a: insulating film, 160: gate electrode layer, 160 a: conductivefilm, 161: gate electrode layer, 161 a: conductive film, 162: gateelectrode layer, 162 a: conductive film, 170: insulating layer, 171:region, 172: region, 173: region, 174: groove portion, 175: insulatinglayer, 175 b: insulating layer, 176: resist mask, 177: resist mask, 200:imaging device, 201: switch, 202: switch, 203: switch, 210: pixelportion, 211: pixel, 212: subpixel, 212B: subpixel, 212G: subpixel,212R: subpixel, 220: photoelectric conversion element, 230: pixelcircuit, 231: wiring, 247: wiring, 248: wiring, 249: wiring, 250:wiring, 253: wiring, 254: filter, 254B: filter, 254G: filter, 254R:filter, 255: lens, 256: light, 257: wiring, 260: peripheral circuit,270: peripheral circuit, 280: peripheral circuit, 290: peripheralcircuit, 291: light source, 300: silicon substrate, 310: layer, 320:layer, 330: layer, 340: layer, 351: transistor, 352: transistor, 353:transistor, 360: photodiode, 361:

anode, 362: cathode, 363: low-resistance region, 365: photodiode, 366:semiconductor layer, 367: semiconductor layer, 368: semiconductor layer,370: plug, 371: wiring, 372: wiring, 373: wiring, 374: wiring, 601:precursor, 602: precursor, 700: substrate, 701: pixel portion, 702: scanline driver circuit, 703: scan line driver circuit, 704: signal linedriver circuit, 710: capacitor wiring, 712: scan line, 713: scan line,714: signal line, 716: transistor, 717: transistor, 718: liquid crystalelement, 719: liquid crystal element, 720: pixel, 721: switchingtransistor, 722: driver transistor, 723: capacitor, 724: light-emittingelement, 725: signal line, 726: scan line, 727: power supply line, 728:common electrode, 750: interposer, 751: chip, 752: terminal, 753: moldresin, 800: RF tag, 801: communication device, 802: antenna, 803: radiosignal, 804: antenna, 805: rectifier circuit, 806: constant voltagecircuit, 807: demodulation circuit, 808: modulation circuit, 809: logiccircuit, 810: memory circuit, 811: ROM, 1189: ROM interface, 1190:substrate, 1191: ALU, 1192: ALU controller, 1193: instruction decoder,1194: interrupt controller, 1195: timing controller, 1196: register,1197: register controller, 1198: bus interface, 1199: ROM, 1200: memoryelement, 1201: circuit, 1202: circuit, 1203: switch, 1204: switch, 1206:logic element, 1207: capacitor, 1208: capacitor, 1209: transistor, 1210:transistor, 1213: transistor, 1214: transistor, 1220: circuit, 1700:substrate, 1701: chamber, 1702: load chamber, 1703: pretreatmentchamber, 1704: chamber, 1705: chamber, 1706: unload chamber, 1711 a:source material supply portion, 1711 b: source material supply portion,1712 a: high-speed valve, 1712 b: high-speed valve, 1713 a: sourcematerial introduction port, 1713 b: source material introduction port,1714: source material exhaust port, 1715: evacuation unit, 1716:substrate holder, 1720: transfer chamber, 1800: panel, 1801: printedwiring board, 1802: package, 1803: FPC, 1804: battery, 2100: transistor,2200: transistor, 2201: insulator, 2202: wiring, 2203: plug, 2204:insulator, 2205: wiring, 2207: insulator, 2210: intermediate layer,2211: semiconductor substrate, 2212: insulator, 2213: gate electrode,2214: gate insulator, 2215: source and drain regions, 3001: wiring,3002: wiring, 3003: wiring, 3004: wiring, 3005: wiring, 3200:transistor, 3300: transistor, 3400: capacitor, 4000: RF tag, 5100:pellet, 5120: substrate, 5161: region, 6000: display module, 6001: uppercover, 6002: lower cover, 6003: FPC, 6004: touch panel, 6005: FPC, 6006:display panel, 6007: backlight unit, 6008: light source, 6009: frame,6010: printed board, 6011: battery, 7101: housing, 7102: housing, 7103:display portion, 7104: display portion, 7105: microphone, 7106: speaker,7107: operation key, 7108: stylus, 7302: housing, 7304: display portion,7311: operation button, 7312: operation button, 7313: connectionterminal, 7321: band, 7322: clasp, 7501: housing, 7502: display portion,7503: operation button, 7504: external connection port, 7505: speaker,7506: microphone, 7701: housing, 7702: housing, 7703: display portion,7704: operation key, 7705: lens, 7706: joint, 7901: utility pole, 7902:display portion, 8000: camera, 8001: housing, 8002: display portion,8003: operation button, 8004: shutter button, 8005: connection portion,8006: lens, 8100: finder, 8101: housing, 8102: display portion, 8103:button, 8121: housing, 8122: display portion, 8123: keyboard, 8124:pointing device, 8200: head-mounted display, 8201: mounting portion,8202: lens, 8203: main body, 8204: display portion, 8205: cable, 8206:battery, 9700: automobile, 9701: car body, 9702: wheels, 9703:dashboard, 9704: lights, 9710: display portion, 9711: display portion,9712: display portion, 9713: display portion, 9714: display portion,9715: display portion, 9721: display portion, 9722: display portion,9723: display portion.

This application is based on Japanese Patent Application serial no.2015-012713 filed with Japan Patent Office on Jan. 26, 2015, JapanesePatent Application serial no. 2015-012718 filed with Japan Patent Officeon Jan. 26, 2015, Japanese Patent Application serial no. 2015-039161filed with Japan Patent Office on Feb. 27, 2015, Japanese PatentApplication serial no. 2015-041682 filed with Japan Patent Office onMar. 3, 2015, Japanese Patent Application serial no. 2015-046870 filedwith Japan Patent Office on Mar. 10, 2015, and Japanese PatentApplication serial no. 2015-053100 filed with Japan Patent Office onMar. 17, 2015, the entire contents of which are hereby incorporated byreference.

1. A semiconductor device comprising: a first insulating layer; a firstoxide insulating layer over the first insulating layer; an oxidesemiconductor layer over the first oxide insulating layer; a sourceelectrode layer and a drain electrode layer over the oxide semiconductorlayer; a second insulating layer over the first insulating layer, thesource electrode layer, the drain electrode layer, and the oxidesemiconductor layer; a second oxide insulating layer over the oxidesemiconductor layer; a gate insulating layer over the second oxideinsulating layer; a gate electrode layer over the gate insulating layer;and a third insulating layer over the second insulating layer, thesecond oxide insulating layer, the gate insulating layer, and the gateelectrode layer, wherein a side surface portion of the second insulatinglayer is in contact with the second oxide insulating layer, wherein thegate electrode layer includes a first region and a second region thathave different widths, wherein the first region is located over thesecond region, and wherein the first region has a width larger than thatof the second region.